Trench Distortion Prevention via Self-Aligned Double Patterning
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Solution Overview
Problem
Conventional semiconductor manufacturing techniques face limitations in downscaling interconnection patterns due to the wavelength constraints of photolithography, leading to distortion in trench and via sidewalls during the damascene process.
Innovation Solution
The method involves using masks with opposite stresses, forming mandrels and spacers, and employing specific etching and ashing processes to pattern and form trenches and vias in a dielectric layer, including the use of SiOC, TiN, and SiON layers, and ashing processes in plasma to prevent distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography is used to pattern interconnections, then interconnection patterns can be formed, but the patterns cannot be scaled down below the wavelength limit of the light source
Solution Approach 1:
The patent applies segmentation by dividing the single photolithography patterning step into multiple sequential patterning steps. First, a preliminary pattern is formed using photolithography, then additional patterns are formed through subsequent deposition and etching steps. This multi-stage approach enables the creation of interconnection patterns with dimensions smaller than the photolithography wavelength limit, effectively overcoming the resolution constraint.
2Ease of manufacture
If conventional damascene process is used to form trenches and vias, then interconnections are formed, but distortion occurs on the sidewalls of trenches and vias
Solution Approach 1:
The patent applies preliminary action by forming a stress control layer between the trench/via pattern and the dielectric layer before the etching process. This layer is deposited and its stress characteristics are controlled in advance to compensate for the stress that would otherwise cause sidewall distortion during the subsequent etching and filling operations. By preparing this stress compensation mechanism beforehand, the final interconnection structures achieve straight, distortion-free sidewalls.
3Manufacturing precision
If masks with opposite stresses are used, then distortion in trench and via sidewalls is reduced, but process complexity increases
Solution Approach 1:
The patent applies parameter changes by controlling the stress parameter of the mask layers. Specifically, the stress control layer is designed with a stress value that is opposite in sign to the stress of the pattern definition mask. This stress parameter control enables the compensation mechanism that prevents sidewall distortion. The stress values are carefully selected and controlled during the deposition process to achieve the desired compensation effect without requiring complex multi-layer mask structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces distortion in trench and via sidewalls, enabling the formation of smaller interconnection patterns and improving the integration density of semiconductor devices.
Implementation Method 1
providing a dielectric layer covered by a first mask and a second mask, wherein the first mask has a first stress, and the second mask has a second stress, wherein the first stress and the second stress are opposite in sign
Implementation Method 2
the mask layer is removed by a first ashing process performed in plasma containing oxygen, followed by preforming a second ashing process in plasma containing nitrogen and hydrogen
Data Source
AI summary
A method of forming trenches and a via by self-aligned double patterning includes providing a dielectric layer covered by an SiOC layer, a TiN layer and a SiON layer from top to bottom. At least two mandrels are formed on the SiOC layer. Later, two spacers are formed respectively at two sidewalls of each mandrel. Subsequently, the mandrels are removed. The SiOC layer and the TiN layer are patterned by using the spacers to form numerous recesses. The spacers are then removed. A mask layer with a via pattern is formed to cover the SiOC layer. A via is formed in the dielectric layer by taking the mask layer as a mask. After that, the mask layer is removed. Finally, numerous trenches are formed in the dielectric layer by taking the SiOC layer and the TiN layer as a mask.