Trench DMOS Transistor Floating Islands Gate-Drain Capacitance
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Solution Overview
Problem
Trench DMOS transistors face a trade-off between low on-state drain-to-source resistance and low gate-to-drain capacitance, where increasing chip size reduces on-state drain-to-source resistance but increases gate-to-drain charge, limiting the maximum switching frequency.
Innovation Solution
Incorporating floating islands between the trench bottom and drain region to reduce gate-to-drain capacitance by partially screening the charge, thereby increasing the maximum switching frequency while maintaining low on-state drain-to-source resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If chip size is increased to reduce on-state drain-to-source resistance, then on-state drain-to-source resistance decreases, but gate-to-drain charge increases
Solution Approach 1:
The drain region is segmented into a first drain region and a second drain region with different doping concentrations. The first drain region has a higher doping concentration than the second drain region, creating distinct functional zones that reduce gate-to-drain capacitance while maintaining low on-state resistance through the heavily-doped first drain region.
Solution Approach 2:
Different regions of the drain are assigned different doping concentrations to optimize local properties. The first drain region near the channel has high doping for low resistance, while the second drain region extends deeper with lower doping to reduce gate-to-drain capacitance, creating local quality variations that resolve the contradiction.
2Productivity
If gate-to-drain capacitance is reduced to increase maximum switching frequency, then maximum switching frequency increases, but on-state drain-to-source resistance may increase
Solution Approach 1:
The drain region is divided into two segments with different doping levels. The first drain region with higher doping concentration maintains low on-state resistance, while the second drain region with lower doping concentration reduces gate-to-drain capacitance, enabling high switching frequency without sacrificing on-state performance.
Solution Approach 2:
The doping concentration parameter is changed across different drain regions. By varying the doping concentration from high in the first drain region to lower in the second drain region, the patent optimizes both electrical resistance and capacitance parameters simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces gate-to-drain capacitance, enhancing the maximum switching frequency and breakdown voltage of the trench DMOS transistor while maintaining low on-state drain-to-source resistance.
Implementation Method 1
Incorporating floating islands between the trench bottom and drain region to reduce gate-to-drain capacitance by partially screening the charge
Data Source
AI summary
A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.