Trench Electrode Structure for Parasitic Thyristor Suppression
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Solution Overview
Problem
In semiconductor devices, particularly in switching regulators, the parasitic PNPN thyristor can turn on due to uncontrolled internal currents during the freewheeling process of the reverse body diode, leading to potential failure, and existing solutions require a large isolation area to prevent this conduction at rated voltage and current.
Innovation Solution
The introduction of an electrode structure with a trench extending from the semiconductor substrate surface, filled with a doped material, which acts as an absorption source for electrons and holes, reducing the risk of parasitic structure activation by recombining carriers and preventing unwanted conduction, thereby minimizing the required isolation area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large isolation area is used to prevent parasitic PNPN thyristor conduction, then reliability is improved, but device area increases
Solution Approach 1:
The patent applies local quality by creating a doped region with specific electrical properties (different doping concentration) in a localized area around the trench structure. This doped region provides targeted carrier recombination capability precisely where needed to suppress parasitic thyristor conduction, rather than requiring a large uniform isolation area. The local modification of material properties enables effective parasitic suppression with minimal area overhead.
Solution Approach 2:
The patent transitions from a two-dimensional planar isolation approach to a three-dimensional structure by introducing a trench that extends vertically into the semiconductor substrate. This vertical dimension allows the isolation structure to intercept and recombine carriers in the depth direction, providing effective parasitic suppression without increasing the lateral footprint. The trench structure utilizes the third dimension (depth) to achieve isolation functionality that would otherwise require larger planar area.
2Reliability
If existing isolation structures are used to block parasitic current, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the isolation function with the existing trench structure (such as a deep N-well or isolation trench already present in the device architecture). By combining the parasitic suppression function with an existing structural element, the patent avoids adding a separate independent isolation structure. The doped region is integrated into the trench, creating a multi-functional structure that provides both mechanical/isolation and electrical/parasitic suppression functions simultaneously.
Solution Approach 2:
The doped region within the trench structure provides self-service by automatically recombining carriers through its inherent electrical properties. The structure does not require external control or additional active components to function - the doped region inherently creates an electric field and carrier recombination mechanism that actively suppresses parasitic current flow. This self-active behavior simplifies the overall device architecture compared to structures requiring external biasing or control circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents the parasitic PNPN thyristor from turning on, enhancing the semiconductor structure's voltage endurance and reducing the overall area needed for isolation, thus improving the reliability and efficiency of the semiconductor device.
Implementation Method 1
filled with a doped material, which acts as an absorption source for electrons and holes, reducing the risk of parasitic structure activation by recombining carriers
Data Source
AI summary
An electrode structure can include: a semiconductor substrate; a trench extending from an upper surface of the semiconductor substrate into the semiconductor substrate; a contact region extending from the upper surface of the semiconductor substrate into the semiconductor substrate; and filling material in the trench, wherein the contact area is in contact with outer sidewalls of the trench.