Trench Electrode Semiconductor Device for Latch-Up Tolerance
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Solution Overview
Problem
IGBTs face a trade-off between conduction ability and short-circuit tolerance due to the parasitic NPN structure, where increasing impurity concentration to improve latch-up tolerance can affect threshold voltage and channel impurity concentration.
Innovation Solution
A semiconductor device with a trench gate structure that includes a deep layer with high P-type impurity concentration to reduce base resistance and improve latch-up tolerance, while maintaining the threshold voltage by forming a three-dimensional channel path, and manufacturing methods to achieve this structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the impurity concentration of the P type layer is increased to reduce base resistance and improve latch-up tolerance, then the short-circuit tolerance is improved, but the impurity concentration of the channel increases which affects the threshold voltage
Solution Approach 1:
The patent divides the P type layer into two distinct regions: a base region with high impurity concentration to reduce base resistance and improve latch-up tolerance, and a channel region with controlled impurity concentration to maintain proper threshold voltage. This segmentation allows each region to be optimized independently for its specific function.
Solution Approach 2:
The patent applies local quality by creating a non-uniform impurity concentration distribution within the P type layer. The base region has high impurity concentration specifically where needed for latch-up protection, while the channel region maintains appropriate impurity levels for voltage control, allowing different parts of the same layer to have different properties.
2Reliability
If the impurity concentration of the P type layer is increased to reduce base resistance, then the short-circuit tolerance is improved, but the conduction ability is lowered due to increased conduction loss
Solution Approach 1:
The patent segments the P type layer into a base region with high impurity concentration for short-circuit protection and a channel region with optimized impurity concentration to maintain low conduction loss. This allows the device to achieve high short-circuit tolerance without sacrificing conduction efficiency.
Solution Approach 2:
The patent implements local quality by concentrating high impurity levels only in the base region where they are needed for latch-up protection, while maintaining appropriate impurity levels in the channel region to minimize conduction loss, thus achieving different optimization goals in different locations.
Data Source
AI summary
According to an embodiment, a semiconductor device 1 includes a semiconductor substrate 50 including an upper surface, a trench electrode 22 provided inside a trench 20 formed on the upper surface, and a trench insulating film 21 provided between the trench electrode 22 and the semiconductor substrate 50. The semiconductor substrate 50 includes a first semiconductor layer of a first conductivity type, a lower end of the trench electrode 22 reaching the first semiconductor layer, a deep layer 19 of a second conductivity type partially provided on the first semiconductor layer in contact with the trench insulating film 21, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer and on the deep layer 19 in contact with the trench insulating film 21, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer above the deep layer 19.