Deep Trench Selective Epitaxy With In-Situ Phosphorus Doping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need in the semiconductor manufacturing process to integrate low temperature epitaxy for growing phosphorous-containing silicon layers to reduce contact resistance of nMOS transistors effectively.
Innovation Solution
A cluster tool is utilized, comprising various chambers for pre-cleaning, plasma-cleaning, deposition, etching, and thermal processing, to form an epitaxial layer on semiconductor devices using specific silicon sources and dopant gases, achieving epitaxial deposition and etch-back processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low temperature epitaxy is used to grow phosphorous-containing silicon layer, then contact resistance of nMOS transistors is reduced, but thermal budget is constrained
Solution Approach 1:
The patent changes the temperature parameter from conventional high temperature (above 700°C) to low temperature (450°C or below) epitaxy process. This parameter change enables phosphorous dopant activation and silicon layer growth simultaneously at low temperature, achieving low contact resistance while preserving the high-K metal gate stack integrity.
Solution Approach 2:
The patent employs a composite approach by combining phosphorous dopant with silicon precursor in the epitaxy process. The phosphorous-containing silicon layer is grown in-situ during the epitaxial growth, creating a doped silicon layer that provides both the conductive pathway and structural integrity needed for low contact resistance applications.
2Manufacturing precision
If conventional high temperature epitaxy is used, then silicon layer growth is achieved, but dopant activation is insufficient
Solution Approach 1:
The patent fundamentally changes the temperature parameter to enable dopant activation at low temperature. By using phosphorous as the dopant source during epitaxy and maintaining the temperature at 450°C or below, the process achieves effective dopant activation without requiring subsequent high-temperature annealing steps that would damage the gate stack.
Solution Approach 2:
The patent performs dopant incorporation during the epitaxial growth process itself, rather than as a separate subsequent step. The phosphorous is introduced along with the silicon precursor, allowing dopant activation to occur concurrently with layer formation at low temperature, before any thermal budget-consuming steps are performed.
3Reliability
If low temperature epitaxy is performed, then high-K metal gate stack is preserved, but process integration complexity increases
Solution Approach 1:
The patent merges the dopant activation step with the silicon layer growth step by performing in-situ doping during low temperature epitaxy. This consolidation eliminates the need for separate high-temperature annealing processes, thereby preserving the high-K metal gate stack while reducing the overall number of process steps despite the specialized low-temperature requirements.
4Reliability
If phosphorous-containing silicon layer is grown at low temperature, then contact resistance is reduced, but etch selectivity requirements increase
Solution Approach 1:
The patent creates a silicon layer with locally optimized properties by incorporating phosphorous during epitaxy. The resulting phosphorous-containing silicon layer has distinct etch characteristics compared to undoped silicon and other materials in the structure, enabling selective etching processes to target specific regions with high precision despite the low temperature growth conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a significant reduction in contact resistance of nMOS transistors by forming a phosphorous-containing silicon epitaxial layer with high dopant activation and improved etch selectivity, while maintaining a low thermal budget.
Implementation Method 1
introducing a liquid precursor and a dopant gas into a reaction chamber and heating the liquid precursor to a temperature sufficient to vaporize the liquid precursor
Implementation Method 2
heating the liquid precursor to a temperature sufficient to vaporize the liquid precursor and decompose the vaporized liquid precursor
Implementation Method 3
a plasma-cleaning chamber coupled to the transfer chamber
Data Source
AI summary
Embodiments of the present disclosure generally relate to methods for forming epitaxial layers on a semiconductor device. In one or more embodiments, methods include removing oxides from a substrate surface during a cleaning process, flowing a processing reagent containing a silicon source and exposing the substrate to the processing reagent during an epitaxy process, and stopping the flow of the processing reagent. The method also includes flowing a purging gas and pumping residues from the processing system, stopping the flow of the purge gas, flowing an etching gas and exposing the substrate to the etching gas. The etching gas contains hydrogen chloride and at least one germanium and/or chlorine compound. The method further includes stopping the flow of the at least one compound while continuing the flow of the hydrogen chloride and exposing the substrate to the hydrogen chloride and stopping the flow of the hydrogen chloride.