Trench ESD Junction Layout for Low-Complexity Semiconductor Integration
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Solution Overview
Problem
Integrating ESD protection devices into semiconductor devices with trench gate transistor devices is challenging due to the need for additional photomasks and complex manufacturing processes, which increase cost and reduce surface area utilization.
Innovation Solution
The integration of trench electrostatic discharge protection devices is achieved by forming PN or NP junctions in parallel trenches connected between metal layers, eliminating the need for a polysilicon layer and optimizing surface area utilization through series and parallel connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon layer is formed above the substrate to create P doped and N doped regions for ESD protection devices, then ESD protection is provided through PN junctions, but an additional photomask is required resulting in increased manufacturing complexity and cost
Solution Approach 1:
The invention merges the formation of ESD protection devices with the existing trench structures used for transistor gates. The same trenches that contain transistor gates are utilized to house ESD protection devices by forming doped regions within these existing trenches, eliminating the need for separate polysilicon layers and additional photomasks.
Solution Approach 2:
The trenches in the semiconductor substrate serve multiple functions: they contain both the gate electrodes for transistor operation and the doped regions for ESD protection. This multi-functional use of the same structural element eliminates the need for dedicated ESD protection structures and reduces manufacturing complexity.
2Device complexity
If short trenches or wells are formed in the semiconductor substrate to create PN junctions for ESD protection, then the need for a polysilicon layer is eliminated, but the process differs from normal trench production increasing complexity and cost
Solution Approach 1:
The formation of doped regions for ESD protection is merged with the standard trench formation process for transistor gates. The same etching and doping steps used to create transistor gates are utilized to create the ESD protection structures, ensuring process compatibility and eliminating the need for separate manufacturing steps.
Solution Approach 2:
The doped regions for ESD protection are formed during the preliminary trench formation process, before the transistor gate electrodes are deposited. This preliminary doping action allows the ESD protection structures to be integrated into the existing manufacturing flow without requiring additional process steps.
3Area of stationary object
If separate wells are formed for ESD protection devices, then PN junctions can be created without polysilicon layer, but surface area utilisation becomes sub-optimal
Solution Approach 1:
The ESD protection devices are merged with the transistor gate trenches, allowing both functions to coexist within the same vertical structure. This merging enables optimal surface area utilization by eliminating the need for separate well structures that would consume additional chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration and reduces manufacturing complexity while providing adequate current carrying capacity and breakdown voltage for ESD protection, improving the overall efficiency and cost-effectiveness of semiconductor devices.
Implementation Method 1
each of the plurality of trenches comprises two or more of the trench electrostatic discharge protection devices, wherein each of the plurality of trench electrostatic discharge protection devices comprises at least one of a PN junction or NP junction formed between one of the first doped regions and the second doped region of the respective trench
Implementation Method 2
Electrostatic discharge (ESD) is the sudden transfer of charge between differently charged objects. Certain electrical components formed as part of semiconductor devices (e.g. MOS based transistor devices) are at risk of being damaged by ESD.
Data Source
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AI summary
A semiconductor device comprising trenches formed in a semiconductor substrate. The trenches comprises a plurality of ESD protection devices formed by PN or NP junctions between respective first doped regions (e.g. a P-doped region) and a second doped region (e.g. an N-doped region). The ESD protection devices are connected in series across the trenches by connection electrodes, which connect the trenches at corresponding points. The two outer trenches comprise ESD protection devices that are connected in parallel to first and second metal layers. The first and second metals between which the ESD protection devices are connected may, for example, be source and gate metal layers. An ESD event causes current to flow through the ESD protection devices.