Trench PN-Junction ESD Layout for Lower-Complexity Fabrication
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Solution Overview
Problem
Integrating ESD protection devices into semiconductor devices with trench gate transistor devices is challenging, requiring additional photomasks and increasing manufacturing complexity and cost, while sub-optimal surface area utilization occurs with existing well formations.
Innovation Solution
A semiconductor device design with trenches containing PN or NP junctions for ESD protection devices, connected in series and parallel across metal layers, eliminating the need for a polysilicon layer and optimizing surface area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon layer is formed above the substrate to create P doped and N doped regions for ESD protection devices, then ESD protection functionality is achieved, but an additional photomask is required resulting in increased manufacturing complexity and cost
Solution Approach 1:
The invention extracts the ESD protection functionality from the traditional polysilicon-based implementation and relocates it into the existing trench structures. By forming P doped and N doped regions directly within the trenches to create PN junctions, the patent eliminates the need for an additional polysilicon layer and its associated photomask, thereby reducing manufacturing complexity while maintaining ESD protection functionality
Solution Approach 2:
The invention merges the ESD protection device formation with the existing trench gate transistor fabrication process. The PN junctions are formed within the same trenches that contain the gate electrodes, combining multiple functions (transistor operation and ESD protection) into a single integrated structure, thus eliminating the need for separate polysilicon processing steps
2Device complexity
If short trenches or wells are formed in the semiconductor substrate to eliminate the polysilicon layer, then manufacturing complexity is reduced, but surface area utilization becomes sub-optimal
Solution Approach 1:
The invention utilizes the vertical dimension of the existing trench structures to accommodate the P doped and N doped regions. By forming the PN junctions within the depth of the trenches rather than requiring additional lateral space, the patent achieves efficient surface area utilization while maintaining the simplified manufacturing process
3Reliability
If different trench geometries are used for ESD protection devices compared to active region trenches, then ESD protection functionality is achieved, but fabrication complexity and cost increase
Solution Approach 1:
The invention makes the existing trench structures multi-functional by using them for both transistor gate formation and ESD protection device creation. The same trench geometry and fabrication processes are used for both purposes, eliminating the need for different trench geometries and reducing fabrication complexity while achieving ESD protection functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances integration and reduces manufacturing complexity by using trenches with PN or NP junctions, providing effective ESD protection with improved surface area utilization and current carrying capacity.
Implementation Method 1
At least some of these diodes are arranged so that in the event of ESD, the current flows in the reverse direction through the diode, and hence the diodes only conduct current in the event of a sudden large voltage spike.
Data Source
AI summary
A semiconductor device has trenches formed in a semiconductor substrate. The trenches have a plurality of ESD protection devices formed by PN or NP junctions between respective first doped regions (e.g., a P-doped region) and second doped regions (e.g., an N-doped region). The ESD protection devices are connected in series across the trenches by connection electrodes, which connect the trenches at corresponding points. The two outer trenches comprise ESD protection devices that are connected in parallel to first and second metal layers. The first and second metal layers between which the ESD protection devices are connected can be source and gate metal layers. An ESD event causes current to flow through the ESD protection devices.