Trench Field-Effect Transistor Layout for Breakdown and On-Resistance
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Solution Overview
Problem
Field-effect transistors face issues with high on-voltage and electric field concentration at the lower end of trenches, which can damage the gate insulating film, and existing designs struggle to balance low on-resistance with high breakdown voltage.
Innovation Solution
The design incorporates p-type breakdown voltage regions with higher impurity concentration, arranged to extend from the upper to the lower end of trenches, spaced from the gate insulating film, and p-type bottom regions to suppress electric field concentration, combined with a manufacturing method using a lattice-shaped mask to stabilize mask formation and facilitate simultaneous formation of body and bottom regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If p-type breakdown voltage regions with higher impurity concentration are introduced to suppress electric field concentration, then breakdown voltage is improved, but on-resistance increases due to additional impurity regions
Solution Approach 1:
The patent applies local quality by creating p-type breakdown voltage regions with higher impurity concentration only in specific locations where electric field concentration occurs (at the lower end of trenches), while maintaining lower impurity concentration in other regions. This localized approach suppresses electric field concentration where needed without unnecessarily increasing on-resistance across the entire device structure.
Solution Approach 2:
The patent utilizes parameter changes by varying the impurity concentration of p-type regions - creating high-concentration breakdown voltage regions near trench bottoms and lower-concentration body regions elsewhere. This parameter variation allows optimization of both breakdown voltage (through high concentration where needed) and on-resistance (through lower concentration in current-carrying paths).
2Reliability
If deep layers extend along a direction intersecting each trench to suppress electric field concentration, then electric field distribution is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the deep layer structure into discrete p-type breakdown voltage regions positioned at specific intervals along the trench length, rather than creating continuous complex three-dimensional deep layers. This segmented approach achieves electric field suppression while simplifying manufacturing through standard ion implantation or diffusion processes.
Solution Approach 2:
The patent transitions from complex three-dimensional deep layer structures to a simplified two-dimensional arrangement of p-type breakdown voltage regions positioned at the lower end of trenches. This dimensional simplification maintains electric field control functionality while significantly reducing manufacturing complexity.
Data Source
AI summary
A field-effect transistor includes: a semiconductor substrate having trenches; and a gate electrode disposed in the trenches. Breakdown voltage regions are provided in each inter-trench range. The breakdown voltage regions are arranged to form rows extending in a first direction intersecting the trenches. The rows are arranged at interval in a second direction parallel to the trenches. Each of the breakdown voltage regions extends from an upper side of a lower end of each of the trenches to a lower side of the lower end of each of the trenches, and is disposed at a distance from a gate insulating film. A drift region is in contact with the gate insulating film at a position between the breakdown voltage region and the gate insulating film.