Trench FET Source Recess Etch for High Density
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Solution Overview
Problem
Conventional semiconductor manufacturing techniques face challenges in achieving high device density and reducing fabrication costs while minimizing power consumption, particularly due to limitations in gate trench spacing and contact-to-trench spacing caused by photoresist implant masks.
Innovation Solution
The use of angled implantations and trench fill insulator layers to form self-aligned N+ source regions adjacent to trenches, allowing for reduced gate trench spacing and increased device density without the need for conventional photoresist implant masks, and subsequent formation of P+ body contact regions that are self-aligned to the N+ source regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photoresist implant masks are used to form source regions and body contact regions, then manufacturing precision is maintained, but gate trench spacing and contact-to-trench spacing are limited, reducing device density
Solution Approach 1:
The patent employs self-aligned ion implantation techniques where the source regions and body contact regions are automatically positioned relative to the gate trenches through sequential implantation steps. The first ion implantation forms source regions that are self-aligned to the gate trenches, and the second ion implantation forms body contact regions that are self-aligned to the source regions, eliminating the need for photoresist masks and enabling reduced spacing between structures.
Solution Approach 2:
The patent transitions from planar mask-based alignment to three-dimensional self-aligned implantation by controlling ion beam angles and depths. By implanting ions at specific angles and depths into the semiconductor substrate, the source and body contact regions are formed in precise spatial relationships to the gate trenches without requiring lateral mask alignment, effectively utilizing the vertical dimension for positioning.
2Productivity
If gate trench spacing is reduced to increase device density, then productivity is improved, but manufacturing precision becomes more difficult to maintain with conventional photoresist methods
Solution Approach 1:
The self-aligned ion implantation process inherently maintains precision even at reduced spacings because the alignment is determined by the implantation geometry and substrate structure rather than by photoresist pattern alignment. The source regions and body contact regions automatically position themselves relative to the gate trenches through the implantation process, eliminating sensitivity to mask alignment errors that would be magnified at smaller feature sizes.
3Ease of manufacture
If conventional photoresist implant masks are used, then manufacturing process is well-established, but fabrication costs and power consumption increase
Solution Approach 1:
The patent removes the photoresist mask step from the fabrication process by directly forming source regions and body contact regions through ion implantation. This extraction of the masking step eliminates the associated materials, processing, and alignment operations, reducing fabrication complexity and cost while maintaining the ability to form precisely positioned doped regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-density vertical field effect transistors with low drain-source on-resistance (Rds(ON)) and allows for tighter gate trench widths, thereby enhancing device density and reducing fabrication costs.
Implementation Method 1
dopants of a first conductivity type are implanted using angled implantations into an upper region of an elevated substrate and trench sidewalls located above the recessed conductive gate electrode structure without using an implant mask to form self-aligned source regions
Data Source
AI summary
A high voltage vertical field effect transistor device (101) is fabricated in a substrate (102, 104) using angled implantations (116, 120) into trench sidewalls formed above recessed gate poly layers (114) to form self-aligned N+ regions (123) adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer (124) formed over the recessed gate poly layers (114), self-aligned P+ body contact regions (128) are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (123), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (135-142) and P+ body contact regions (130-134).