Trench Semiconductor Fill With Barrier Layer for Void Containment
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Solution Overview
Problem
Void formation in polysilicon layers within trenches of electronic devices leads to disruptions and defects, as seams in the polysilicon deposition can coalesce into voids that migrate towards the trench sidewall, causing variations in device function and integration issues.
Innovation Solution
A process involving the formation of a barrier layer to prevent voids from migrating into a void-free semiconductor layer, where the semiconductor layer partially fills the trench and an insulating layer fills the remainder, with thermal operations to manage void formation and diffusion, ensuring no void is completely surrounded by the semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If polysilicon is deposited to fill trenches, then the trench can be filled with conductive material, but voids form at the trench sidewall interface causing device defects
Solution Approach 1:
A liner layer is deposited on the trench sidewalls before polysilicon deposition. This preliminary action creates a controlled interface that prevents void formation when polysilicon is subsequently deposited, eliminating the reliability issue while maintaining complete trench fill.
Solution Approach 2:
The liner layer acts as an intermediary between the trench sidewall and the polysilicon fill material. This intermediate layer prevents direct contact and adhesion issues that cause void formation, allowing complete fill without defects.
2Reliability
If multiple polysilicon depositions are used to eliminate voids, then void formation can be reduced, but process complexity increases
Solution Approach 1:
Instead of multiple polysilicon depositions, a single liner layer is deposited beforehand. This preliminary action eliminates voids in a single deposition step, maintaining process simplicity while achieving complete void elimination.
Solution Approach 2:
The liner layer serves as a mediator that prevents void formation during a single polysilicon deposition, avoiding the need for multiple deposition steps and process complexity.
3Reliability
If anneal time and temperature are increased to eliminate voids, then void coalescence can be reduced, but other process steps are interfered with
Solution Approach 1:
The liner layer is deposited before polysilicon to prevent void formation from the start. This preliminary preventive measure eliminates the need for extended annealing, maintaining process integration without interference.
Solution Approach 2:
Instead of using thermal energy to try to eliminate voids after formation (which interferes with other steps), the liner layer converts the potential harm of void formation into a benefit by preventing it at the interface, allowing normal anneal conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in electronic devices with more reproducible electronic characteristics across substrates and production lots, as voids are contained within the insulating layer and do not affect the semiconductor layer, enhancing device reliability and consistency.
Implementation Method 1
exposing the second semiconductor layer to radiation sufficient to allow a void within the second semiconductor layer to migrate toward the barrier layer
Implementation Method 2
forming a barrier layer within the trench after forming the first semiconductor layer... allow a void within the second semiconductor layer to migrate toward the barrier layer
Data Source
AI summary
In an aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and forming a first semiconductor layer within the trench and along the sidewall. In an embodiment, the process can further include forming a barrier layer within the trench after forming the first semiconductor layer; forming a second semiconductor layer within the trench after forming the barrier layer, wherein within the trench, first and second portions of the second semiconductor layer contact each other adjacent to a vertical centerline of the trench; and exposing the second semiconductor layer to radiation sufficient to allow a void within second semiconductor layer to migrate toward the barrier layer. In another embodiment, after forming a semiconductor within the trench, the process can further include forming an insulating layer that substantially fills a remaining portion of the trench.