Trench Gate Semiconductor Structure With Air Gaps for Low RC Delay
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing parasitic capacitance and current leakage as they become more integrated, leading to increased RC delay and interference with normal transistor operation.
Innovation Solution
A semiconductor device is fabricated with a trench structure that includes a gate insulating layer, gate electrode, and air gap to reduce parasitic capacitance and current leakage by interposing an air gap between the semiconductor layer and the substrate, using a sacrificial layer that is removed to create this gap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are highly integrated and miniaturized, then device density and performance are improved, but parasitic capacitance and current leakage increase
Solution Approach 1:
The device structure is segmented into distinct regions separated by air gaps, isolating the semiconductor layer from direct contact with substrates. This segmentation reduces parasitic capacitance by eliminating continuous conductive paths between components while maintaining high integration density through vertical stacking.
Solution Approach 2:
Air gaps are introduced as intermediary spaces between the semiconductor layer and substrates. These air gaps act as electrical insulators with minimal parasitic capacitance, mediating the interaction between closely spaced components and reducing harmful capacitive coupling while allowing high-density integration.
2Productivity
If device size is reduced to increase integration, then more devices fit on chip, but RC delay increases due to higher parasitic capacitance
Solution Approach 1:
The continuous substrate structure is segmented by introducing air gaps that electrically isolate different device regions. This segmentation reduces the capacitive load on interconnects and transistors, thereby reducing RC delay even as device density increases and dimensions shrink.
Solution Approach 2:
The dielectric parameter between adjacent conductive elements is changed from solid material (higher permittivity) to air (lower permittivity). This parameter change reduces parasitic capacitance values, directly reducing RC delay and improving signal propagation speed in highly integrated circuits.
3Speed
If transistors are miniaturized to improve performance, then operating speed increases, but current leakage increases interfering with normal operation
Solution Approach 1:
Air gaps serve as intermediary insulating layers between the semiconductor layer and substrates, preventing direct current leakage paths. The air medium provides electrical isolation that blocks parasitic current flow while maintaining the miniaturized transistor structure needed for high operating speed.
Solution Approach 2:
The harmful direct contact interface between semiconductor layer and substrate is extracted and replaced with air gap isolation. This removal of the leakage-prone interface eliminates a major current leakage path while preserving the compact device structure required for high-speed operation.
Data Source
AI summary
A semiconductor device includes: a semiconductor layer, a gate insulating layer, and a gate electrode sequentially formed in a trench formed to a predetermined depth from a first surface of a first substrate; a third substrate bonded to a second surface opposite to the first surface of the first substrate; and an air gap interposed between the semiconductor layer and the first substrate and between the semiconductor layer and the third substrate.