Trench-Gate Semiconductor Layout for Gate Finger Avalanche Resistance
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high avalanche resistance due to electric field concentration at the gate finger portion, which leads to premature breakdown during high-voltage applications, making it difficult to preferentially induce avalanche breakdown at the active portion.
Innovation Solution
The semiconductor device incorporates a trench-gate structure with a second conductive-type impurity region and an electric field relaxation region formed deeper than the gate finger trench, reducing the pitch of the impurity region at the gate finger portion and alleviating electric field concentration, thereby allowing avalanche breakdown to occur preferentially at the active portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate finger portion is made with the same structure as the active portion, then the manufacturing process is simplified, but the avalanche resistance is reduced due to electric field concentration at the gate finger portion
Solution Approach 1:
The patent applies local quality by introducing a guard ring structure specifically at the gate finger portion with different impurity concentration and depth characteristics compared to the active portion. The guard ring has a lower doped concentration and extends deeper into the substrate, creating localized electric field relaxation only where needed at the gate finger, while leaving the active portion structure unchanged for optimal device performance.
2Manufacturing precision
If the pitch of the impurity region at the gate finger portion is increased, then the manufacturing precision is improved, but the electric field concentration is exacerbated leading to premature breakdown
Solution Approach 1:
The patent changes the parameters of the impurity region at the gate finger portion by reducing the doped concentration and increasing the depth of the guard ring structure. This parameter modification allows the impurity region to extend deeper into the substrate with a relaxed pitch, thereby reducing electric field concentration without requiring tight pitch control during manufacturing.
3Stability of the object's composition
If the gate finger portion is designed to have the same breakdown resistance as the active portion, then the device uniformity is improved, but the avalanche breakdown cannot be preferentially induced at the active portion
Solution Approach 1:
The patent implements local quality by creating a distinct guard ring structure at the gate finger portion with different electrical characteristics (lower doped concentration, greater depth) compared to the active portion. This localized structural differentiation ensures that the gate finger portion has higher breakdown resistance, thereby enabling avalanche breakdown to occur preferentially at the active portion while maintaining overall device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances avalanche resistance by reducing electric field concentration at the gate finger portion and increasing the density of the impurity region, allowing the semiconductor device to withstand higher avalanche currents and maintain reliability under high-voltage conditions.
Implementation Method 1
a second conductive-type electric field relaxation region which is formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches
Implementation Method 2
it is necessary to cause avalanche breakdown by a pn junction of an active portion
Data Source
AI summary
The semiconductor device of the present invention includes a semiconductor layer which includes an active portion and a gate finger portion, an MIS transistor which is formed at the active portion and includes a gate trench as well as a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench at the gate finger portion, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region which is formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.