Trench-Gate BiMOS Structure for High Current Density
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Solution Overview
Problem
BiMOS semiconductor devices face limitations in achieving high current density due to low impurity concentration in the n− drift layer, leading to increased depletion layer field intensity and higher on-voltage in IGBTs.
Innovation Solution
Incorporating a parallel pn layer with alternately joined n− drift and p pillar layers, along with high-resistance layers between the p base and n+ source layers, allows for a uniform depletion layer field intensity, enabling higher impurity concentration and improved current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the n− drift layer has low impurity concentration to achieve high voltage resistance, then voltage resistance is improved, but current density decreases
Solution Approach 1:
The drift region is segmented into multiple alternating n-type and p-type layers (n− drift layer, p pillar layer, n− drift layer, etc.) forming a multi-layered structure. This segmentation allows each layer to contribute differently to the overall performance, with the n-type layers providing voltage resistance and the p-type layers enabling higher impurity concentration regions that improve current density.
Solution Approach 2:
Different regions of the drift structure have different impurity concentrations and doping types. The n− drift layers have low impurity concentration for voltage resistance, while the p pillar layers and other n-type regions can have higher impurity concentrations to enhance current density locally without compromising overall voltage resistance.
2Stress or pressure
If the n− drift layer has low impurity concentration to reduce depletion layer field intensity, then field intensity is reduced, but on-voltage increases
Solution Approach 1:
The drift region is divided into multiple alternating n-type and p-type layers, creating multiple depletion regions. This segmentation distributes the electric field across multiple interfaces, reducing the field intensity at any single interface while maintaining overall voltage resistance.
Solution Approach 2:
The invention changes the doping parameters by introducing alternating n-type and p-type layers with different impurity concentrations. The p-type layers have higher impurity concentration than the n-type drift layers, creating a parameter gradient that reduces depletion layer field intensity at critical interfaces while allowing higher overall current density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in enhanced current density and reduced potential barriers, facilitating easier electron flow and improved performance in BiMOS semiconductor devices.
Implementation Method 1
an inversion layer 14c is generated in a portion of the p base layer 14a in the vicinity of the gate electrode 17 when a gate voltage positive with respect to the emitter/source electrode 18 is applied to the gate electrode 17
Implementation Method 2
an electron current 21a flows from the collector/drain electrode 11 to the emitter/source electrode 18 through the n+ drain layer 12, the n− drift layer 13, the inversion layer 14c, and the n+ source layer 14b
Implementation Method 3
electron currents 21b and 21c flow and an electron current 21d flows from the collector/drain electrode 11 to the emitter/source electrode 18 through the n+ drain layer 12, the n− drift layer 13, the p base layer 14a, and the n+ source layer 14b. A hall current 22 also flows from the p base layer 14a to the n− drift layer 13
Data Source
AI summary
Provided is an n-channel BiMOS semiconductor device having a trench gate structure, the n-channel BiMOS semiconductor device including: an n+ drain layer; a parallel pn layer including n− drift and p pillar layers joined alternately; a composite layer including a p base layer and an n+ source layer, the n+ drain layer, the parallel pn layer, and the composite layer being provided in order; a high-resistance layer provided between a portion of the p base layer above the p pillar layer and the n+ source layer; and a high-resistance layer provided between the p pillar layer and the p base layer, the p pillar layer having an impurity concentration lower than that of the n− drift layer.