Trench Gate Structure for Faster Switching and Breakdown Immunity

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Solution Overview

Problem

Existing semiconductor devices with trench gate structures face challenges in dielectric breakdown immunity and switching speed due to electric field concentration and capacitance issues between the gate and field plate electrodes.

Innovation Solution

The semiconductor device incorporates a second insulating film that extends closer to the surface than the first insulating film, creating a thicker, more concave gate electrode portion, which increases the distance between the field plate and gate electrodes, enhancing dielectric breakdown immunity and reducing capacitance, while the gate contact part is designed to avoid short-circuits by not positioning between the gate wiring layer and the thinner gate electrode portion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the gate electrode is made thinner to reduce capacitance and improve switching speed, then switching speed is improved, but dielectric breakdown immunity deteriorates due to increased electric field concentration

Engineering Contradiction:
Improveswitching speedVSAvoiddielectric breakdown immunity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The gate electrode is designed with varying thickness: a thinner first portion (50-200 nm) above the field plate electrode to reduce capacitance and improve switching speed, and a thicker second portion (200-500 nm) above the semiconductor layer to reduce electric field concentration and improve dielectric breakdown immunity. This local variation in thickness allows simultaneous optimization of both switching speed and reliability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The gate electrode transitions from a uniform two-dimensional structure to a three-dimensional structure with varying thickness. The concave portion creates a vertical dimension variation that allows different thicknesses at different locations, enabling the gate electrode to simultaneously achieve low capacitance (thinner region) and high breakdown immunity (thicker region).

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If the distance between gate electrode and field plate electrode is increased to reduce capacitance, then switching speed is improved, but device area increases

Engineering Contradiction:
Improveswitching speedVSAvoiddevice area
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The second insulating film is positioned only in specific regions where it is needed to create the thicker gate electrode portion, rather than uniformly across the entire device. This localized approach allows capacitance reduction in critical areas while minimizing the overall device area expansion.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The second insulating film is nested within the gate electrode structure, creating a concave portion that effectively increases the gate-to-field-plate distance without adding external volume. The insulating film is embedded in the gate electrode material, allowing compact integration.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20250022952A1Semiconductor device
Publication Date: 2025.01.16 KK TOSHIBA
  • US20250022952A1 patent drawing
  • US20250022952A1 patent drawing
  • US20250022952A1 patent drawing

AI summary

The trench structure part includes a field plate electrode, a first insulating film, a second insulating film, the second insulating film extending to be more proximate to the first surface than the first insulating film, a gate electrode including a first portion located on the second insulating film, and a second portion located on the first insulating film, the second portion being thicker than the first portion, and a third insulating film. The gate contact part extends from the gate wiring layer toward the second portion and contacts the second portion. The gate contact part is not positioned between the first portion and the gate wiring layer. The first portion is positioned adjacent, in a second direction orthogonal to the first direction, to a lower end portion of the gate contact part contacting the second portion.