Trench-Gate Semiconductor Device Buried Source Alignment

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Solution Overview

Problem

The existing trench-MOSFET manufacturing process is sensitive to process variations, leading to unreliable breakdown voltage performance due to difficulties in aligning oxide layers and resulting in deteriorated leakage and breakdown behavior, attributed to discontinuities in the oxide structure.

Innovation Solution

The solution involves accurately positioning the buried polysilicon source region by using a second trench at a well-defined depth within the first trench, and thermally growing all oxide layers to form a contiguous oxide region, thereby improving alignment and reducing discontinuities between the oxide layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If deposited oxide layers are used in the known manufacturing process, then the manufacturing process can be completed, but the oxide layers exhibit discontinuities at intersection regions leading to deteriorated leakage and breakdown behavior

Engineering Contradiction:
Improvebreakdown voltage performanceVSAvoiddiscontinuities in oxide structure
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent replaces the mechanical deposition process (PVD/CVD) with a thermal oxidation process. Instead of depositing oxide layers that create discontinuities at intersections, the invention uses thermal growth of oxide layers from the silicon substrate, which naturally forms continuous, uniform oxide regions without deposition-induced discontinuities at intersection regions.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter of oxide layer formation from deposition to thermal oxidation. This parameter change transforms the oxide layer quality from discontinuous (deposition) to continuous (thermal oxidation), eliminating the harmful discontinuities at intersection regions while maintaining the required oxide thickness and electrical properties.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the known manufacturing process is used, then the trench-MOSFET can be manufactured, but the process is sensitive to process variations leading to unreliable breakdown voltage performance

Engineering Contradiction:
Improvebreakdown voltage performanceVSAvoidalignment of oxide layers
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent replaces the deposition-based oxide formation with thermal oxidation, which is inherently more precise and less sensitive to process variations. Thermal oxidation grows oxide uniformly from the substrate surface, eliminating alignment issues between multiple deposited layers and their intersection regions, thereby improving manufacturing precision and reliability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the uniformity and reliability of the trench-gate semiconductor device by reducing sensitivity to process variations and improving breakdown voltage performance, while also mitigating leakage current and enhancing gate quality.

Implementation Method 1

thermally growing all oxide layers to form a contiguous oxide region

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Data Source

PatentEP4033542A1Trench-gate semiconductor device
Publication Date: 2022.07.27 NEXPERIA BV
  • EP4033542A1 patent drawingFigure 1
  • EP4033542A1 patent drawingFigure 2A~2D
  • EP4033542A1 patent drawingFigure 2E~2H

AI summary

The present Invention relates to a trench-gate semiconductor device and a manufacturing method therefor. A trench-gate semiconductor device is provided of which each unit cell comprises a first trench, and a second trench extending from a bottom of the first trench. The semiconductor device further comprises a gate oxide layer arranged on a first side wall of the first trench, a second oxide layer arranged on a second side wall and bottom of the second trench, a first polysilicon region arranged inside the first trench, separated from the first side wall by the gate oxide layer, and forming a gate of the unit cell. In addition, the semiconductor device comprises a second polysilicon region arranged inside the second trench, separated from the second side wall and bottom of the second trench by the second oxide layer, and forming a buried source of the unit cell, and a third oxide layer arranged in between the first polysilicon region and the second polysilicon region.