Trench Gate Semiconductor Contact Doping for Stable Threshold Voltage
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Solution Overview
Problem
Conventional semiconductor devices with trench gate structures face issues with latch-up tolerance due to increased resistance in the contact between the gate and trench, leading to fluctuations in gate threshold voltage, which are difficult to stabilize with existing manufacturing methods.
Innovation Solution
A method of manufacturing semiconductor devices that involves forming a first trench, burying it with an insulated gate electrode structure, and implanting impurity ions diagonally into the side wall surface of a second trench to create a contact region, while also implanting ions into the bottom surface to form a contact region, thereby reducing lateral diffusion of p-type impurity ions and stabilizing the electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If p-type impurity ions are implanted into the contact trench to reduce contact resistance, then contact resistance decreases, but gate threshold voltage fluctuates due to lateral diffusion of impurity ions
Solution Approach 1:
The patent divides the contact trench into two distinct regions: a first region with p-type impurity ions for low contact resistance, and a second region with n-type impurity ions to suppress lateral diffusion. This segmentation allows each region to perform its specific function independently, resolving the contradiction between reducing contact resistance and preventing gate threshold voltage fluctuation.
Solution Approach 2:
The patent applies preliminary anti-action by introducing n-type impurity ions into the second region of the contact trench before final device operation. This n-type region acts as a barrier that preemptively counteracts the lateral diffusion of p-type impurity ions, preventing them from reaching the gate trench and causing threshold voltage fluctuations.
2Manufacturing precision
If the mesa part width is increased to stabilize electrical properties, then gate threshold voltage stability improves, but device size increases
Solution Approach 1:
The patent extracts the function of stabilizing gate threshold voltage from the mesa part width and relocates it to the impurity ion distribution structure within the contact trench. By taking out the stabilization function from the geometric dimension (mesa width) and implementing it through material composition (impurity ion distribution), the device can maintain electrical stability with reduced dimensions.
Solution Approach 2:
The patent transitions from controlling electrical properties through horizontal dimension (mesa part width) to controlling them through vertical dimension (impurity ion distribution depth and concentration profiles). The n-type impurity region at a specific depth in the contact trench provides stabilization without requiring increased lateral dimensions.
3Reliability
If contact trench area is increased to reduce contact resistance, then contact resistance decreases, but device complexity increases
Solution Approach 1:
The patent applies local quality by creating regions with different impurity concentrations and types within the contact trench. The first region has high p-type impurity concentration for low resistance, while the second region has n-type impurity to control diffusion. This local differentiation allows the contact trench to achieve low resistance without requiring overall area expansion, thereby avoiding increased device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses fluctuations in gate threshold voltage, allowing for the minimization of semiconductor devices by reducing contact resistance and maintaining stable electrical properties, without requiring ultra-shallow implantation devices.
Implementation Method 1
a method of manufacturing a semiconductor device including: forming a first trench from an upper surface side of a semiconductor substrate of a first conductivity-type; burying the first trench with an insulated gate electrode structure; forming a base region of a second conductivity-type at an upper part of the semiconductor substrate so as to be in contact with the first trench; forming a first main electrode region of the first conductivity-type at an upper part of the base region so as to be in contact with the first trench; forming a second trench by removing a part of the first main electrode region; implanting first impurity ions of the first conductivity-type entirely into a side wall surface of the second trench from a diagonally upper side; implanting second impurity ions of the second conductivity-type into a bottom surface of the second trench so as to form a contact region of the second conductivity-type at a bottom of the second trench; and forming a second main electrode region of the second conductivity-type on a bottom surface side of the semiconductor substrate
Data Source
AI summary
A method of manufacturing a semiconductor device includes: forming a first trench from an upper surface side of a semiconductor substrate; burying the first trench with an insulated gate electrode structure; forming a base region at an upper part of the semiconductor substrate so as to be in contact with the first trench; forming a first main electrode region at an upper part of the base region so as to be in contact with the first trench; forming a second trench by removing a part of the first main electrode region; implanting first impurity ions entirely into a side wall surface of the second trench from a diagonally upper side; implanting second impurity ions into a bottom surface of the second trench to form a contact region at a bottom of the second trench; and forming a second main electrode region on a bottom surface side of the semiconductor substrate.