Trench Gate Semiconductor Structure for Narrow Self-Aligned Contact Trenches
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Solution Overview
Problem
Existing semiconductor devices, such as trench gate field effect transistors, face challenges in reducing the width of the channel region and contact trench to increase current density, as conventional contact lithography technologies like the 0.18 μm power platform process struggle to accurately form narrower features.
Innovation Solution
A semiconductor device and manufacturing method involving a protruding source base structure oxidized by thermal oxidation to form a self-alignment source region with a narrow top and wide bottom, allowing for the formation of a narrower contact trench through anisotropic etching, enabling the creation of a semiconductor device with higher current density by reducing the channel and contact trench widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional contact lithography technology (0.18 μm power platform process) is used, then the manufacturing process is simple and well-established, but the minimum feature size that can be accurately formed is limited to approximately 0.3 μm for contact trenches
Solution Approach 1:
The patent performs preliminary actions by forming the source region with a wider bottom portion before forming the contact trench. This preliminary structuring enables subsequent self-alignment processes that achieve narrower contact trenches without requiring more complex lithography tools. The source region is formed first with specific dimensional characteristics that facilitate the later formation of the narrow contact trench through self-aligned etching processes.
Solution Approach 2:
The patent employs self-aligned processes where previously formed structures (the source region and channel region) automatically serve as alignment references for subsequent steps. The contact trench is formed using the source region as a self-aligned mask, eliminating the need for additional complex lithography alignment steps. This self-service mechanism enables precise sub-0.3 μm contact trench formation using existing lithography capabilities.
2Productivity
If the first width W1 of the channel region is reduced to increase current density, then the current density increases, but the second width W2 of the contact trench becomes smaller and harder to form accurately
Solution Approach 1:
The patent transitions from a single-dimensional width reduction approach to a multi-dimensional structural solution. Instead of simply reducing contact trench width in one dimension, the invention creates a three-dimensional source region structure with different widths at different depths (wider bottom, narrower top). This dimensional transformation allows the contact trench to be formed with precise sub-0.3 μm width by leveraging the vertical dimension and self-alignment, thereby maintaining manufacturing accuracy while achieving the required narrow dimensions for high current density.
Solution Approach 2:
The patent changes the dimensional parameters of the source region, specifically creating a structure where the bottom width is greater than the top width. This parameter transformation enables the contact trench to be formed with a narrow width (less than 0.3 μm) by using the wider bottom portion of the source region as a self-aligned reference during etching, thus achieving precise contact trench formation that would otherwise be impossible with conventional lithography limits.
3Productivity
If the second width W2 of the contact trench is reduced below 0.3 μm, then the current density can be further increased, but conventional lithography technology cannot accurately form such narrow features
Solution Approach 1:
The patent introduces the source region with its wider bottom portion as an intermediary structure that mediates between the lithography capability and the desired narrow contact trench. This intermediary structure serves as a self-aligned mask and reference during the contact trench formation process, enabling the formation of sub-0.3 μm features using conventional lithography tools. The intermediary source region structure bridges the gap between existing manufacturing capabilities and the required narrow dimensions for high current density applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively forms narrower channel and contact trenches, overcoming the limitations of conventional lithography technologies and enhancing the current density of semiconductor devices.
Implementation Method 1
A semiconductor device and manufacturing method involving a protruding source base structure oxidized by thermal oxidation to form a self-alignment source region with a narrow top and wide bottom
Data Source
AI summary
A semiconductor device and a manufacturing method thereof is provided. The device includes a semiconductor layer having a first and second surface opposing each other; a trench gate in the semiconductor layer, extends in a first direction parallel to the first and second surface, and from the first surface to an interior of the layer, and has a gate open end distant from the second surface; a source region of a first conductivity type and a channel region of a second conductivity type, orthographic projections of the source region and the channel region on the second surface at least partially overlap with each other in a depth direction of the trench gate, the source region having a source open end distant from the second surface, and the farther the source open end is from the second surface, the smaller a width of the source open end in the second direction.