Trench Gate Dielectric Layout for Co-Planar HVT and LVT Stacks
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Solution Overview
Problem
The challenge in semiconductor manufacturing is achieving substrate planarization for both high-voltage and low-voltage transistors on the same substrate without damaging the high-voltage gate stack during chemical mechanical polishing, due to differences in gate dielectric thickness.
Innovation Solution
Forming a gate dielectric within a trench in the substrate to control the gate oxide thickness, ensuring the top gate stack surfaces of high-voltage and low-voltage transistors are co-planar, thereby preventing over-polishing during CMP processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a CMP process is used to planarize the substrate surface, then the low-voltage gate stack can be properly formed, but the high-voltage gate stack is over-polished and damaged
Solution Approach 1:
The patent applies local quality by forming a trench structure specifically in the high-voltage region to create a localized depth adjustment. This allows the gate dielectric to be formed at different depths in different regions, enabling the high-voltage gate stack to be protected while maintaining overall planarity for the CMP process.
Solution Approach 2:
The patent introduces a vertical dimension solution by creating a trench (a depth variation) in the high-voltage region. This dimensional change allows the gate dielectric thickness to vary vertically in different regions, solving the planarity conflict without compromising either region's functionality.
2Reliability
If the gate dielectric thickness is increased for high-voltage transistors, then high-voltage device performance is improved, but the gate stack becomes non-co-planar with low-voltage transistors
Solution Approach 1:
The patent segments the substrate into distinct regions (high-voltage and low-voltage areas) with different gate dielectric thicknesses. By dividing the gate dielectric structure into region-specific thicknesses, the patent allows each region to have optimized dielectric thickness while maintaining overall co-planarity through the trench structure.
Solution Approach 2:
The patent applies local quality by forming a trench structure specifically in the high-voltage region to create a localized depth adjustment. This allows the gate dielectric to be formed at different depths in different regions, enabling the high-voltage gate stack to be protected while maintaining overall planarity for the CMP process.
3Productivity
If the gate dielectric thickness is reduced for low-voltage transistors, then low-voltage device performance is improved, but the high-voltage gate stack becomes vulnerable to over-polishing
Solution Approach 1:
The patent applies preliminary action by forming the trench structure in the high-voltage region before depositing the gate dielectric. This pre-prepared depth variation ensures that when the gate dielectric is formed, the high-voltage region has additional thickness built in, which will later protect it during the CMP process while allowing the low-voltage region to have thinner dielectric for optimal performance.
Data Source
AI summary
A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.