Trench Gate Dielectric for CMP Planarization
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Solution Overview
Problem
Chemical mechanical polishing (CMP) processes in semiconductor manufacturing often fail to achieve planarization across high-voltage and low-voltage transistor regions, leading to over-polishing and damage of high-voltage transistor gate stacks due to height differences in gate dielectric layers.
Innovation Solution
Forming a gate dielectric within a trench in the substrate allows for controlled gate oxide thickness, ensuring the top gate stack surfaces of high-voltage and low-voltage transistors are co-planar, thereby preventing over-polishing during CMP processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a CMP process is used to planarize the substrate, then the low-voltage transistor gate stack is properly polished, but the high-voltage transistor gate stack is over-polished and damaged
Solution Approach 1:
The patent introduces a vertical dimension solution by forming a trench structure beneath the high-voltage transistor gate stack. This allows the gate dielectric to extend vertically into the trench, creating a stepped configuration where the high-voltage gate stack has additional height. This dimensional change enables both high-voltage and low-voltage transistor gate stacks to reach the same top surface level, allowing uniform CMP polishing without over-polishing the high-voltage devices.
2Reliability
If the gate dielectric thickness is increased for high-voltage transistors, then the high-voltage transistor performance is improved, but the top gate stack surfaces become non-co-planar
Solution Approach 1:
The patent segments the substrate into distinct regions: a first region containing high-voltage transistors with thicker gate dielectric and a second region containing low-voltage transistors with thinner gate dielectric. By spatially separating these different dielectric thickness requirements into different substrate regions, the patent enables each region to be optimized for its specific voltage requirements while maintaining overall process compatibility through the trench structure.
Solution Approach 2:
The trench structure provides a vertical dimension solution that allows the high-voltage gate dielectric to achieve greater effective thickness for improved performance while the top surfaces of both high-voltage and low-voltage gate stacks remain co-planar. The trench enables the thicker dielectric to be accommodated beneath the high-voltage region without protruding above the common top surface.
3Productivity
If device geometry is scaled down, then production efficiency is improved and costs are reduced, but substrate planarization complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the trench structure and depositing the gate dielectric material into the trench before completing the gate stack formation. This preliminary preparation of the substrate topology ensures that subsequent CMP polishing can be performed uniformly across the entire wafer, simplifying the overall manufacturing process despite the added initial complexity of trench formation.
Data Source
AI summary
A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.