Buried Gate Transistor Trench Structure Using a Dipole Inducing Layer
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Solution Overview
Problem
Gate-induced drain leakage (GIDL) significantly affects the performance of buried gate-type transistors, and existing technologies have not effectively addressed this issue to enhance their performance.
Innovation Solution
A semiconductor device with a buried gate structure is developed, featuring a gate dielectric layer, a first gate electrode, a second gate electrode, and a dipole inducing layer. The dipole inducing layer is positioned between the gate electrodes and the gate dielectric layer to reduce the effective work function of the second gate electrode, thereby suppressing GIDL. This structure includes a trench in the substrate with a first source/drain region and a second source/drain region, where the dipole inducing layer is formed between the first and second gate electrodes and the gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate electrode is used for high performance operation, then the transistor performance is improved, but gate-induced drain leakage (GIDL) increases
Solution Approach 1:
The patent applies local quality by introducing a dipole inducing layer with specific dipole moments at the interface between the gate electrode and gate dielectric layer. This layer creates a localized electric field that modifies the potential distribution only in the critical region near the drain, reducing GIDL without affecting the overall gate control. The dipole inducing layer is positioned specifically where the electric field gradient is highest, providing targeted suppression of leakage while maintaining high-performance operation.
Solution Approach 2:
The dipole inducing layer acts as an intermediary between the metal gate electrode and the gate dielectric layer. It mediates the electric field interaction by introducing dipole moments that counteract the harmful GIDL effect. This intermediate layer allows the metal gate to maintain its high-performance characteristics while the dipole layer suppresses the leakage, effectively decoupling the conflicting requirements.
2Reliability
If the threshold voltage is controlled for high-performance operation, then the transistor performance is improved, but GIDL characteristic worsens
Solution Approach 1:
The patent changes the electrical parameters at the gate-dielectric interface by introducing a dipole inducing layer with controlled dipole moments. This layer modifies the effective work function and threshold voltage characteristics locally, allowing independent optimization of threshold voltage control and GIDL suppression. The dipole moment density and orientation are carefully controlled to achieve the desired parameter changes without compromising either threshold voltage stability or leakage performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of the dipole inducing layer effectively reduces GIDL, enhancing the performance of buried gate-type transistors by adjusting the threshold voltage and lowering the gate sheet resistance, thereby improving the overall operational efficiency.
Implementation Method 1
a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer
Data Source
AI summary
A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.