Trench Gate Structure Alignment Using Dual-Side Dopant Implantation

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Solution Overview

Problem

Existing semiconductor device manufacturing processes face challenges in aligning the current spread region with the gate structure, requiring high implantation energy levels that can cause damage and inefficiencies, limiting tool redundancy and increasing power consumption.

Innovation Solution

A method is introduced where the current spread region is formed after trench formation, with dopants implanted through the top surface and bottom of the semiconductor body to align vertically with the gate structure, reducing the required implantation energy level and enabling lower energy tools for efficient alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If high implantation energy levels are used to align the current spread region with the gate structure, then alignment precision is improved, but device reliability deteriorates due to damage and inefficiencies

Engineering Contradiction:
Improvealignment precisionVSAvoiddevice reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming the current spread region before forming the gate structure. This sequence allows the current spread region to be pre-positioned with proper vertical alignment, eliminating the need for high-energy implantation through the gate structure and thereby preventing damage while maintaining alignment precision.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If high implantation energy levels are used to form the current spread region, then alignment is achieved, but power consumption increases

Engineering Contradiction:
Improvealignment precisionVSAvoidpower consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The current spread region is formed in advance before the gate structure is created. This preliminary formation allows lower energy implantation processes to be used, significantly reducing power consumption while still achieving the required vertical alignment between the current spread region and the subsequent gate structure.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If high implantation energy levels are used, then alignment is achieved, but tool redundancy decreases

Engineering Contradiction:
Improvealignment precisionVSAvoidtool redundancy
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

By forming the current spread region before the gate structure, the patent enables the use of lower energy implantation tools. This approach increases tool redundancy because a wider variety of dopant implanting tools can be used, including those with lower maximum energy capabilities, thereby improving manufacturing flexibility and adaptability.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces power consumption, increases ion flux, and enhances tool redundancy by allowing the use of a wider range of dopant implanting tools, while maintaining precise alignment and improved electrical performance.

Implementation Method 1

The second implantation process may comprise implanting first dopants, through a top surface of the semiconductor body, to form a first portion of the current spread region, and implanting second dopants, through a bottom of the trench, to form a second portion of the current spread region

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20260068240A1Semiconductor device with gate structure and current spread region
Publication Date: 2026.03.05 INFINEON TECHNOLOGIES AG
  • US20260068240A1 patent drawing
  • US20260068240A1 patent drawing
  • US20260068240A1 patent drawing

AI summary

According to some embodiments, a method for manufacturing a semiconductor device is provided. One or more first implantation processes are performed to form an implanted region, of a first conductivity type, in a semiconductor body. A trench is formed in the semiconductor body. After forming the trench, a second implantation process is performed to form a current spread region, of a second conductivity type, in the semiconductor body. The second implantation process includes implanting first dopants, through a top surface of the semiconductor body, to form a first portion of the current spread region, and implanting second dopants, through a bottom of the trench, to form a second portion of the current spread region. A gate structure is formed in the trench. A vertical position of the first portion of the current spread region matches a vertical position of the gate structure. The second portion of the current spread region underlies the gate structure.