Trench Gate Semiconductor Device Self-Aligned Drain Formation
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Solution Overview
Problem
Existing methods for integrating trench-gate semiconductor devices into integrated circuits often require thick epitaxial or buried doped layers, which can have undesirable effects on other devices formed on the same wafer, making it challenging to achieve seamless integration.
Innovation Solution
The method employs silicon surface migration techniques to form a self-aligned drain region below the trench, eliminating the need for thick epitaxial or buried doped layers, using hydrogen annealing to transform initial trenches into shallower trenches with buried cavities, and forming a drain region within these cavities, with optional insulating material filling to create a buried isolation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick epitaxial or buried doped layers are formed to create the drain region, then the drain region can be properly formed, but other devices on the same wafer are adversely affected
Solution Approach 1:
The drain region formation is segmented into two independent parts: (1) a shallow doped layer formed by ion implantation through the trench opening, and (2) a deep doped region formed by diffusion from the shallow layer during a subsequent thermal anneal. This segmentation allows the drain region to be formed without requiring thick epitaxial or buried doped layers that would adversely affect other devices on the wafer.
Solution Approach 2:
The trench is formed preliminarily before the drain region formation process. The trench serves as a pre-formed structure that guides the ion implantation and subsequent diffusion processes, enabling the drain region to be formed precisely where needed without affecting surrounding devices. The trench also provides physical isolation during the thermal anneal process.
2Manufacturing precision
If ion implantation is used to form the drain region through the trench, then precise placement is achieved, but dopant diffusion during annealing may affect adjacent structures
Solution Approach 1:
The trench structure serves as a beforehand cushioning barrier that confines dopant diffusion during the thermal anneal process. The trench walls physically limit the lateral diffusion of dopants, preventing them from reaching adjacent structures. This cushioning effect is established before the diffusion process begins, ensuring precise dopant placement even during high-temperature annealing.
Solution Approach 2:
The shallow doped layer formed by ion implantation acts as an intermediary between the ion implantation process and the deep diffusion process. It serves as a controlled source of dopants that diffuse during annealing, mediating the transition from precise implantation to broader diffusion while maintaining spatial control through the trench geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the integration of trench-gate devices into planar integrated circuits without the adverse effects of thick epitaxial or buried doped layers, enhancing device compatibility and manufacturing efficiency.
Implementation Method 1
The annealing step causes transformation of the initial trenches, such that the semiconductor body instead defines corresponding shallower trenches with a common cavity extending laterally below them
Implementation Method 2
the method includes a further step of filling the lower cavity with an insulating material, for example by oxidation of its sidewalls or deposition, to form the buried isolation layer
Data Source
Figure 1~3C
Figure 4A~7C
Figure 8A~11C
AI summary
A trench-gate semiconductor device configuration is provided which is suitable for incorporation in integrated circuits, together with methods for its manufacture. A self-aligned drain region (12a) is provided below the device trench (18). The manufacturing methods include etching an initial trench into a semiconductor body (8), and annealing so as to cause migration of material such that a shallower trench with a cavity (36) below it are formed. The drain region is then formed in the cavity. A further cavity (52) may be used to form a buried isolation layer (56) below the drain region, e.g by thermal oxidation.