Trench-Gate Semiconductor Edge Structure Against Dicing Cracks
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Solution Overview
Problem
Semiconductor devices experience cracking and chipping in the outer peripheral portion due to external forces and temperature variations, leading to reliability issues and physical breakage.
Innovation Solution
A semiconductor device design incorporating a semiconductor substrate with trench gates, first amorphous layers on one side surface, and second amorphous layers on the other, where the angles and thicknesses of these layers are strategically configured to enhance structural integrity and reduce stress concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a semiconductor device is cut from the semiconductor wafer using conventional methods, then individual semiconductor devices can be obtained for use, but cracking and chipping occur in the outer peripheral portion due to external forces applied by cleavage
Solution Approach 1:
An amorphous layer is formed on the outer peripheral portion of the semiconductor substrate before the dicing process. This preliminary action prepares the surface to withstand the external forces during cleavage, preventing cracking and chipping that would otherwise occur during the manufacturing process.
Solution Approach 2:
The physical and chemical properties of the outer peripheral surface are changed by forming an amorphous layer, which has different characteristics from the crystalline semiconductor substrate. This parameter change in the surface structure enables the material to resist the mechanical stresses of dicing while maintaining overall device functionality.
2Productivity
If the semiconductor device undergoes switching operation causing temperature variation, then the device performs its power control function, but physical breakage and characteristic deterioration may originate from cracks or chips in the outer periphery portion
Solution Approach 1:
The amorphous layer acts as a protective cushion formed beforehand on the outer peripheral portion. During temperature variations from switching operations, this layer absorbs and distributes thermal stresses, preventing the initiation and propagation of cracks that would lead to device failure.
3Reliability
If the outer peripheral portion is strengthened to prevent cracking and chipping, then reliability is improved, but the device size and structural complexity increase
Solution Approach 1:
Instead of strengthening the entire semiconductor device, the amorphous layer is applied locally only to the outer peripheral portion where cracking and chipping occur during dicing. This localized approach improves reliability at the critical stress points without adding unnecessary complexity or size to the overall device structure.
Data Source
AI summary
It is an object of the present disclosure to provide a semiconductor device having improved reliability of an outer peripheral portion. In plan view, a first angle between a first side surface and a direction of extension of a trench gate is smaller than a second angle between a second side surface and the direction of extension of the trench gate, or the first side surface is parallel to the direction of extension of the trench gate. A thickness of a first amorphous layer in a direction from the first side surface toward an inside of a semiconductor substrate is different from a thickness of a second amorphous layer in a direction from the second side surface toward the inside of the semiconductor substrate.