Trench-Gate FET Layout to Cut On-Resistance and Gate Capacitance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Trench-gate field effect transistors face challenges in reducing on-resistance and miniaturization due to increased capacitance between source and gate electrodes and limitations in metal contact electrode configuration, which hinder further development of high-frequency power components.

Innovation Solution

The design incorporates an epitaxial lamination structure with trenches of varying widths and a unique gate electrode configuration, including a Y-shaped arrangement, along with insulation and contact electrodes to reduce capacitance and enhance miniaturization, while maintaining low on-resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the density of the trenches is increased to reduce on-resistance and turn-on energy loss, then the miniaturization of the trench-gate field-effect transistor is facilitated, but the capacitance between the source electrodes and the gate electrodes is increased, causing a Miller effect

Engineering Contradiction:
Improveon-resistanceVSAvoidcapacitance between source and gate electrodes
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

The gate electrode is segmented into multiple parts (first gate electrode portion, second gate electrode portion, third gate electrode portion) positioned at different depths and locations within the trench structure. This segmentation allows the gate to control different regions independently, reducing the overall capacitance between source and gate while maintaining effective control over the channel, thereby reducing the Miller effect even with high trench density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a conventional planar gate structure to a three-dimensional trench gate structure with varying widths at different depths (first trench region, neck trench region, second trench region). This dimensional change enables the gate to extend deeper into the substrate and control the channel more efficiently, reducing on-resistance without proportionally increasing the gate-source capacitance that causes the Miller effect

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Strength

If the width of the mesa between two adjacent trenches is decreased to increase trench density, then the on-resistance is reduced, but the configuration of the metal contact electrodes becomes more limited, restricting further miniaturization

Engineering Contradiction:
Improveon-resistanceVSAvoidmetal contact electrode configuration
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The metal contact electrodes are configured to extend into the trenches and make contact with the gate and source electrodes at different depths within the three-dimensional trench structure. This vertical dimensionality allows the contact electrodes to access multiple conductive elements without requiring additional lateral space, enabling continued miniaturization of the mesa width while maintaining proper electrical connections

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The contact electrode structure is nested within the trench structure, with contact regions positioned at different depths corresponding to the gate and source electrode locations. This nested configuration allows multiple electrical connections to be achieved within the confined lateral space, reducing the impact on mesa width and enabling further miniaturization

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20230411470A1Trench-gate field effect transistor
Publication Date: 2023.12.21 FORCE MOS TECH CO LTD
  • US20230411470A1 patent drawing
  • US20230411470A1 patent drawing
  • US20230411470A1 patent drawing

AI summary

A trench-gate field effect transistor includes a plurality of trenches, a plurality of gate electrode units, and a plurality of source electrode units. Each of the trenches has a first trench region, a second trench region having a width less than that of the first trench region, and a neck trench region extending between the first trench region and the second trench region. Each of the gate electrode units includes a pair of first gate electrode portions disposed in the first trench region, a pair of second gate electrode portions disposed in the neck trench region, and a third gate electrode portion disposed in the second trench region. Each of the source electrode units includes a first source electrode portion disposed between a pair of the first gate electrode portions, and a second source electrode portion connected to the first source electrode portion.