Trench Gate FET Self-Aligned Source Contact
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional trench gate FET designs are limited by photolithography design rules, restricting the spacing between trenches and the enhancement of the reduced surface field (RESURF) effect, which affects the breakdown voltage (BVdss) and on-resistance (RDSon) characteristics.
Innovation Solution
The approach involves forming buried body regions and self-aligned source contact regions through blanket ion implant processes, eliminating the need for contact masks and allowing closer trench spacing, along with edge termination structures that maintain the RESURF condition at the device edges with shallower body regions in termination cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If masks are used for formation of isolation regions and source contacts, then manufacturing precision is maintained, but spacing between trenches is increased limiting RESURF effect
Solution Approach 1:
The patent extracts and eliminates the mask formation steps from the fabrication process. By using self-aligned source contacts where the source contact region is formed directly adjacent to the trench sidewall without requiring a separate contact mask, and removing the isolation region mask, the process complexity is reduced while maintaining or improving spacing between trenches.
Solution Approach 2:
The invention implements self-alignment where the source contact region automatically positions itself relative to the trench structure through the formation sequence. The source contact region is formed in the mesa region adjacent to the trench sidewall, and the trench structure itself serves as the alignment reference, eliminating the need for external mask alignment.
2Ease of manufacture
If conventional mask-based formation is used, then source contact alignment is achieved, but additional processing steps are required
Solution Approach 1:
The patent removes the contact mask formation step from the fabrication sequence. The source contact alignment is achieved through the self-aligned geometry where the source contact region is formed directly adjacent to the trench sidewall, eliminating the need for a separate contact opening etch step through a contact mask.
Solution Approach 2:
The source contact region is formed in advance as part of the mesa region structure, before final contact opening steps. By pre-positioning the source contact region adjacent to the trench during the doping or deposition process, the alignment is established early in the fabrication sequence, reducing subsequent processing steps.
3Reliability
If trench spacing is reduced to enhance RESURF effect, then breakdown voltage and on-resistance improve, but mask design rules are violated
Solution Approach 1:
The patent extracts the limiting mask design rules from the fabrication constraints. By eliminating the isolation region mask and contact mask, the minimum spacing requirements imposed by photolithography design rules are removed, allowing trenches to be spaced closer together to maximize the RESURF effect while maintaining proper source contact formation.
Solution Approach 2:
The invention changes the fabrication parameters by transitioning from mask-based patterning to self-aligned formation. This allows the trench spacing parameter to be reduced below the conventional photolithography design rule limits, as the critical dimensions are no longer constrained by mask minimum feature sizes and spacing requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the RESURF effect, achieving lower RDSon for a given BVdss and providing effective edge termination without additional processing steps, thereby improving the overall performance and reliability of trench gate FETs.
Implementation Method 1
forming buried body regions and self-aligned source contact regions through blanket ion implant processes
Implementation Method 2
Such transistors often leverage the reduced surface field (RESURF) effect to achieve a relatively low on resistance (RDSon) while maintaining a relatively high breakdown voltage (BVdss)
Data Source
AI summary
A semiconductor device includes a substrate and a semiconductor layer having a first conductivity type. The semiconductor device further includes first and second trenches extending into the semiconductor layer from a surface of the semiconductor layer, each of the first and second trenches including a corresponding gate electrode. The semiconductor device further includes a body region having a second conductivity type different than the first conductivity type and a source contact region having the first conductivity type. The body region is disposed in the semiconductor layer below the surface of the semiconductor layer and between a sidewall of the first trench and an adjacent sidewall of a second trench. The source contact region is disposed in the semiconductor layer between the body region and the surface of the semiconductor layer and extending between the sidewall of the first trench and the corresponding sidewall of the second trench.