Trench Buried Gate Structure for Lower GIDL Memory Cells
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Solution Overview
Problem
Gate Induced Drain Leakage (GIDL) occurs in semiconductor devices due to the overlap of gate electrodes and impurity regions, leading to reduced operational reliability and increased interference between memory cells.
Innovation Solution
A semiconductor device design featuring a trench structure with a lower gate electrode, an upper gate electrode, and a thicker dielectric layer between them, formed using thermal oxidation and atomic layer deposition processes, which reduces the effective electric field and allows the lower and upper gate electrodes to receive different voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buried gate structure with overlapping gate electrodes and impurity regions is used, then device functionality is achieved, but gate induced drain leakage (GIDL) increases and operational reliability deteriorates
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) separated by a gate dielectric layer. This segmentation breaks the continuous gate structure into discrete portions, allowing independent voltage control and reducing the overlap effect between gate and impurity regions that causes GIDL, thereby improving operational reliability
Solution Approach 2:
A gate dielectric layer is introduced as an intermediary between the gate electrode segments and the impurity regions. This dielectric layer acts as a mediator that reduces the direct electric field interaction between the gate and impurity regions, suppressing GIDL while maintaining the necessary device functionality
2Object-generated harmful factors
If a thicker dielectric layer is used between gate electrodes to reduce GIDL, then effective electric field is reduced and GIDL decreases, but device complexity increases
Solution Approach 1:
The gate dielectric layer is selectively positioned only in specific regions where GIDL is most problematic, rather than uniformly throughout the entire gate structure. This localized approach reduces GIDL in critical areas while minimizing the overall structural complexity and maintaining simplicity in non-critical regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces GIDL, extends data retention time, and enhances the operational reliability of semiconductor devices by minimizing interference between word-lines in memory cells while maintaining good device performance.
Implementation Method 1
a first dielectric layer partially disposed between the lower gate electrode and the upper gate electrode
Implementation Method 2
The second dielectric layer is disposed by a thermal oxidation process
Implementation Method 3
The first dielectric layer is disposed by an atomic layer deposition (ALD) process
Data Source
AI summary
A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The trench includes a lower gate electrode, an upper gate electrode over the lower gate electrode and a first dielectric layer partially disposed between the lower gate electrode and the upper gate electrode. The lower gate electrode and the upper gate electrode are spaced apart from the substrate by different distances, and the lower gate electrode and the upper gate electrode are configured to receive different voltages.