Trench Gate Dielectric Structure for Lower GIDL Memory Cells
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Solution Overview
Problem
Gate-induced drain leakage (GIDL) in semiconductor devices increases operational unreliability due to the overlap of gate electrodes and impurity regions, exacerbated by the presence of passing gates in isolation regions, which can lead to interference between word-lines and reduced data retention times.
Innovation Solution
A semiconductor device design featuring a thicker dielectric layer between the gate electrodes and the substrate, with a constant thickness for the dielectric layer between the lower gate electrode and the substrate, and a capping layer positioned further from the substrate than the gate electrodes, reducing the effective electric field and optimizing subthreshold swing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate electrode is disposed adjacent to impurity regions in a trench, then the buried gate structure can be formed to control the active region, but Gate induced drain leakage (GIDL) increases due to the overlap between the gate electrode and impurity regions
Solution Approach 1:
A first dielectric layer is introduced as an intermediary between the upper gate electrode and the capping layer. This dielectric layer acts as a mediator that reduces the effective electric field between the gate electrode and impurity regions, thereby suppressing GIDL while maintaining the functional overlap needed for device operation
Solution Approach 2:
The patent changes the physical parameters of the gate structure by introducing a dielectric layer with specific thickness and material properties. This modifies the electric field distribution and reduces the strength of the harmful interaction between the gate electrode and impurity regions, reducing GIDL
2Object-generated harmful factors
If a thicker dielectric layer is formed in the trench, then the effective electric field is reduced and GIDL is reduced, but the device structure becomes more complex
Solution Approach 1:
The dielectric structure is segmented into multiple functional layers: a first dielectric layer between the gate electrode and capping layer to reduce GIDL, and a second dielectric layer between the lower gate electrode and substrate to optimize electrical characteristics. This segmentation allows each layer to perform its specific function with optimized thickness, reducing overall structural complexity while effectively suppressing GIDL
3Reliability
If the distance between the capping layer and substrate is increased, then the effective electric field is reduced and operational reliability is improved, but the trench depth and manufacturing complexity increase
Solution Approach 1:
Instead of uniformly increasing the distance between capping layer and substrate throughout the entire trench, the patent applies dielectric layers selectively in specific regions. The first dielectric layer is positioned where it most effectively reduces GIDL between the gate electrode and impurity regions, while the second dielectric layer optimizes the lower gate electrode characteristics. This localized approach achieves reliability improvement without unnecessarily increasing overall trench depth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces GIDL, minimizes interference between memory cells, extends data retention times, and enhances operational reliability by increasing channel ions flow between doped regions.
Implementation Method 1
Forming a thicker dielectric layer in the trench may reduce the effective electric field and consequently reduce GIDL
Implementation Method 2
The dielectric layer between the lower gate electrode and the substrate can have a constant thickness, which helps to optimize the subthreshold swing and decrease the threshold voltage
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method includes forming a trench in a substrate; disposing an upper gate electrode in the trench; disposing a first dielectric layer on the upper gate electrode in the trench; and disposing a capping layer on the first dielectric layer in the trench.