Trench Gate IGBT Collector Segmentation for Low ON Voltage

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Solution Overview

Problem

Trench gate IGBTs face challenges in balancing load short circuit withstand and ON voltage, with increasing collector current to reduce ON voltage leading to increased residual carriers and deteriorating switching off loss performance, and increasing collector region concentration to enhance load short circuit withstand affecting switching off loss.

Innovation Solution

A semiconductor device with a trench gate IGBT featuring a lightly-doped P+ type first collector region and a heavily-doped P++ type second collector region, where the P++ type second collector region is strategically placed to offset injected electrons and suppress the Kirk effect, ensuring low ON voltage and high load short circuit withstand without degrading switching off loss performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the collector current is increased to reduce ON voltage, then the ON voltage decreases, but the residual carriers increase and switching off loss performance deteriorates

Engineering Contradiction:
ImproveON voltageVSAvoidswitching off loss
Core Design Contradiction:
Use of energy by moving objectVSLoss of energy

Solution Approach 1:

The collector region is segmented into two distinct regions: a first collector region with lower impurity concentration and a second collector region with higher impurity concentration. This segmentation allows each region to perform different functions - the first region contributes to current conduction while the second region suppresses the Kirk effect and reduces residual carriers, thereby resolving the contradiction between low ON voltage and low switching off loss.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different impurity concentrations are applied locally within the collector region. The second collector region, positioned adjacent to the N- type drift region, has a higher impurity concentration than the first collector region. This local quality variation enables the second region to effectively suppress the Kirk effect and reduce residual carriers without increasing the overall collector current, thus achieving low ON voltage with minimal switching off loss.

Inventive Principle:
Principle #3Local quality

2Reliability

If the concentration of the collector region is increased to ensure load short circuit withstand, then the load short circuit withstand improves, but switching off loss performance deteriorates

Engineering Contradiction:
Improveload short circuit withstandVSAvoidswitching off loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The collector region is divided into two segments with different impurity concentrations. The second collector region with higher concentration is strategically positioned to suppress the Kirk effect during load short circuit conditions, ensuring reliable withstand capability. The first collector region with lower concentration minimizes residual carriers during normal operation, maintaining low switching off loss performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A localized high-concentration second collector region is created adjacent to the N- type drift region to specifically address load short circuit withstand requirements. This local quality enhancement provides the necessary reliability during short circuit conditions while the overall collector region maintains lower average concentration to preserve switching off loss performance.

Inventive Principle:
Principle #3Local quality

3Reliability

If a single high-concentration collector region is used to suppress the Kirk effect, then load short circuit withstand improves, but the device complexity increases

Engineering Contradiction:
Improveload short circuit withstandVSAvoidcollector region structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The collector region is segmented into two distinct regions with different impurity concentrations, where the second collector region with higher concentration is positioned adjacent to the N- type drift region. This segmentation provides effective Kirk effect suppression and load short circuit withstand capability while maintaining a relatively simple two-region structure that is easier to manufacture than more complex multi-layer configurations.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces ON voltage while maintaining high load short circuit withstand and preventing deterioration in switching off loss performance by strategically placing the P++ type second collector region to offset electrons and suppress the Kirk effect.

Implementation Method 1

a P type impurity is ion-implanted into the back surface side of the semiconductor substrate to form a P+ type first collector region. Then, after patterning of a resist film formed by application on the back surface of the semiconductor substrate, a P type impurity is ion-implanted into the back surface side of the semiconductor substrate with the patterned resist film as a mask to form a P++ type second collector region.

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS10147810B2Semiconductor device and method of manufacturing same
Publication Date: 2018.12.04 RENESAS ELECTRONICS CORP
  • US10147810B2 patent drawing
  • US10147810B2 patent drawing
  • US10147810B2 patent drawing

AI summary

To achieve a semiconductor device equipped with a low ON voltage and high load short circuit withstand trench gate IGBT. A collector region on a back surface of a semiconductor substrate is comprised of a relatively lightly-doped P+ type first collector region and a relatively heavily-doped P++ type second collector region. The P++ type second collector region includes, in plan view, interfaces between a first trench having therein a first linear trench gate electrode and an N+ type emitter region formed on the side surface of the first trench and between a second trench having therein a second linear trench gate electrode and an N+ type emitter region formed on the side surface of the second trench. This enables electrons injected from the surface side of the semiconductor substrate to reach the P++ type second collector region and offset, with them, holes injected from the back surface side of the semiconductor substrate.