Trench Gate IGBT With Independent Double-Gate Driving
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Solution Overview
Problem
High-power insulated gate bipolar transistors (IGBTs) face challenges in reducing on-resistance while minimizing switching loss, as increasing carrier concentration in the n-type drift region during the on-state can lead to delayed carrier discharge during turn-off, thereby increasing turn-off time and switching loss.
Innovation Solution
The semiconductor device incorporates a trench gate structure with multiple gate electrodes and a control circuit that independently controls gate voltages, allowing for double gate driving by changing the second gate voltage before the first gate voltage, forming a p-type inversion layer in the barrier region to facilitate hole discharge and reduce on-resistance and switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the carrier concentration of the n-type drift region is increased to reduce on-resistance, then the on-resistance decreases, but the turn-off time becomes long and switching loss increases
Solution Approach 1:
The gate structure is segmented into multiple independent gate electrodes (first gate electrode and second gate electrode) that can be controlled separately. This allows independent optimization of different regions: the first gate controls the channel for low on-resistance, while the second gate controls carrier discharge for fast turn-off, resolving the contradiction between low on-resistance and fast turn-off time
Solution Approach 2:
The second gate electrode is used to preliminarily discharge carriers from the n-type drift region before the main turn-off operation. By applying a negative voltage to the second gate in advance, carriers are extracted from the drift region, which reduces the stored charge and enables faster subsequent turn-off, thereby reducing turn-off time and switching loss while maintaining low on-resistance
2Loss of time
If double gate driving is implemented to reduce switching loss, then switching time is shortened, but device complexity increases
Solution Approach 1:
Multiple gate electrodes are merged into a single trench structure, sharing the same gate insulating film and physical space. This integrated design reduces fabrication complexity compared to completely separate gate structures, while still enabling independent control for reduced switching time
Solution Approach 2:
The multiple gate electrodes serve multiple functions: the first gate electrode controls channel formation for low on-resistance, while the second gate electrode controls carrier discharge for fast turn-off. This multi-functionality within a unified trench gate structure reduces overall device complexity while achieving short switching time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces on-resistance and switching loss by optimizing carrier concentration and discharge timing, while also suppressing destruction from avalanche breakdown and improving long-term characteristics.
Implementation Method 1
a gate electrode provided in the trench; a semiconductor layer having a barrier region, a drift region, and a base region in this order from the frontside toward the backside, the gate electrode being electrically connected to the barrier region and being applied with a gate voltage that forms a p-type inversion layer in the barrier region
Implementation Method 2
electrons are injected from the n-type emitter region to the n-type drift region, and at the same time, holes are injected from the collector region to the n-type drift region. Accordingly, a current having electrons and holes as carriers flows between the collector electrode and the emitter electrode
Data Source
AI summary
A semiconductor device of one embodiment including: a semiconductor layer with first and second planes, first and second trenches, a third trench beside the first trench, a fourth trench beside the second trench, and first to fourth semiconductor regions; first to fourth gate electrodes in the first to fourth trenches, respectively; a first electrode on the first plane, a first contact area with the semiconductor layer between the first trench and the third trench being larger than a second contact area with the semiconductor layer between the third trench and the fourth trench, a third contact area with the semiconductor layer between the second trench and the fourth trench being larger than the second contact area; a second electrode on the second plane; a first gate electrode pad connected to the first and second gate electrodes; and a second gate electrode pad connected to the third and fourth gate electrodes.