Trench Gate IGBT With Non-Uniform Insulation
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Solution Overview
Problem
Semiconductor devices with trench gate type insulated gate bipolar transistors (IGBTs) face challenges in reducing on-state voltage and maintaining switching controllability due to the carrier storage layer restricting hole discharge, leading to reduced controllability when switching from the off state to the on state.
Innovation Solution
The semiconductor device features a semiconductor substrate with a drift layer, a base layer, a carrier storage layer with higher impurity concentration, and trenches filled with a gate insulation film, where the thickness of the gate insulation film on the sidewall of the trench near the collector layer is thicker than on the opening side, restricting gate potential variation and reducing on-state voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a carrier storage layer (CS layer) is formed between the base layer and the drift layer to reduce on-state voltage, then the on-state voltage is reduced, but the switching controllability is reduced when switching from the off state to the on state
Solution Approach 1:
The gate insulation film is designed with non-uniform thickness, where the thickness at the bottom of the trench (near the CS layer) is greater than the thickness at the opening portion. This local variation in thickness creates different electrical characteristics in different regions of the gate structure, allowing the bottom region to restrict hole accumulation while maintaining overall low on-state voltage
Solution Approach 2:
The thickness parameter of the gate insulation film is changed from uniform to non-uniform distribution. Specifically, the film thickness is increased at the bottom region near the CS layer interface, which changes the electrical field distribution and restricts hole accumulation in that specific region, thereby improving switching controllability while preserving the voltage-reducing effect of the CS layer
2Loss of energy
If the CS layer restricts hole discharge to reduce on-state voltage, then the on-state voltage is reduced, but the gate potential changes rapidly due to hole accumulation near the CS layer
Solution Approach 1:
The gate insulation film thickness is locally increased at the bottom region where it contacts the CS layer. This creates a region with different electrical properties that prevents rapid gate potential changes caused by hole accumulation, while the rest of the structure maintains the low on-state voltage characteristic
Solution Approach 2:
The thicker portion of the gate insulation film at the trench bottom acts as an intermediary layer between the gate electrode and the CS layer. This intermediary structure moderates the interaction between holes and the gate, preventing direct charge accumulation effects that would cause rapid gate potential changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces on-state voltage and restricts the reduction of switching controllability by preventing rapid changes in gate potential during the switching process, improving the device's performance in power switching applications.
Implementation Method 1
the thickness of at least a portion of a part of the gate insulation film arranged on a sidewall of each trench disposed on a collector layer side from a peak position, at which the impurity concentration of the carrier storage layer is highest, is thicker than a thickness of another part of the gate insulation film arranged on the sidewall of each trench disposed on an opening portion side of the trench from the peak position
Implementation Method 2
the resistance of the drift layer is reduced by conductivity modulation, so that the device becomes an on state
Implementation Method 3
an inversion layer (i.e., a channel) having the N conductive type is formed at a portion of the base layer contacting with the trench
Implementation Method 4
an accumulation layer of an electron is formed at a portion of the drift layer and a portion of the CS layer contacting with the trench
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer and a carrier storage layer over the drift layer; a collector layer on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and the carrier storage layer and reaching the drift layer; a gate electrode on an insulation film in each trench; and an emitter region in a surface portion of the base layer contacting each trench. A thickness of at least a portion of a part of the gate insulation film on a sidewall of each trench on a collector layer side from a peak position, at which the impurity concentration of the carrier storage layer is highest, is thicker than a thickness of another part of the gate insulation film on the sidewall of an opening portion side of the trench from the peak position.