Trench Gate IGBT Structure for Lower Switching Loss
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Solution Overview
Problem
There is a demand to reduce switching loss in insulated gate bipolar transistors (IGBTs).
Innovation Solution
A trench gate type IGBT design with multiple gate electrodes and trench structures is implemented, allowing independent control of transistors to optimize switching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional IGBT structure is used, then device simplicity is maintained, but switching loss cannot be effectively reduced
Solution Approach 1:
The base region is divided into multiple portions (first base region portion, second base region portion, third base region portion) with different impurity concentrations and thicknesses. This segmentation allows independent optimization of carrier storage and switching characteristics, reducing switching loss while maintaining manageable device complexity through systematic regional differentiation.
Solution Approach 2:
Different regions of the base region are assigned different impurity concentrations (first concentration in first portion, second concentration in second portion, third concentration in third portion) and different thicknesses. This local quality variation enables tailored carrier injection and storage characteristics in specific regions, achieving reduced switching loss without requiring complete structural redesign.
2Loss of time
If base region thickness is reduced to shorten turn-on time, then switching speed improves, but carrier storage capacity decreases
Solution Approach 1:
The base region is segmented into portions with different thicknesses, where the first base region portion has a first thickness and the second base region portion has a second thickness different from the first. This segmentation allows the device to achieve fast turn-on through thinner regions while maintaining adequate carrier storage in other regions, resolving the contradiction between speed and capacity.
Solution Approach 2:
The invention varies both thickness parameters and impurity concentration parameters across different base region portions. By changing these parameters locally, the device achieves rapid turn-on in specific regions while preserving overall carrier storage capacity, effectively resolving the time-capacity trade-off.
3Productivity
If impurity concentration in base region is increased to improve carrier injection, then turn-on characteristics improve, but turn-off loss increases
Solution Approach 1:
The base region is divided into portions with different impurity concentrations (first, second, and third concentrations). This segmentation enables high carrier injection efficiency in regions with higher impurity concentration while maintaining lower turn-off loss in regions with lower impurity concentration, effectively resolving the contradiction between turn-on performance and turn-off loss.
Solution Approach 2:
Different impurity concentrations are assigned to different local regions of the base region. This local quality variation allows optimized carrier injection in specific areas without proportionally increasing turn-off loss across the entire device, achieving improved productivity with controlled energy loss.
Data Source
AI summary
A semiconductor device according to an embodiment includes a first trench, a first gate electrode in the first trench, a second trench, a second gate electrode provided in the second trench, a third trench, a third gate electrode in the third trench, a first electrode pad electrically connected to the first gate electrode, a second electrode pad electrically connected to the second gate electrode, and a third electrode pad electrically connected to the third gate electrode, in which a thickness of a conductive semiconductor region opposed to the third gate electrode is smaller than a thickness of a conductive semiconductor region opposed to the first gate electrode, and in which the thickness of the conductive semiconductor region opposed to the third gate electrode is smaller than a thickness of a conductive type semiconductor region opposed to the second gate electrode.