Trench Gate IGBT With MOS Electrode for Carrier Discharge
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Solution Overview
Problem
In IGBTs, there is a trade-off relationship between turn-off loss Eoff and saturation voltage Vce (sat) related to conduction loss, where reducing one parameter worsens the other, making it difficult to simultaneously minimize both.
Innovation Solution
A semiconductor device with a trench gate structure and a MOS transistor configuration, where the MOS transistor is used to control carrier discharge in the IGBT, allowing for independent management of turn-off and conduction losses by using a trench electrode and a MOS electrode with specific semiconductor layers and insulating films to optimize carrier accumulation and discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If carrier concentration is increased to reduce saturation voltage Vce (sat), then conduction loss is reduced, but turn-off loss Eoff increases due to longer carrier discharge time
Solution Approach 1:
The invention divides the gate control into two independent gates: a first gate (trench gate) that controls carrier accumulation for conduction, and a second gate (MOS gate) that controls carrier discharge during turn-off. This segmentation allows independent optimization of conduction and turn-off characteristics without mutual interference, resolving the trade-off between conduction loss and turn-off loss
Solution Approach 2:
The second gate (MOS gate) acts as an intermediary that specifically manages carrier discharge from the drift layer. By introducing this intermediate control mechanism, the patent enables rapid carrier removal during turn-off without affecting the carrier accumulation controlled by the first gate, thus reducing turn-off loss while maintaining low conduction loss
2Loss of energy
If a p-type floating layer is added to accumulate carriers and reduce saturation voltage Vce (sat), then conduction loss is reduced, but turn-off loss Eoff increases due to difficulty in discharging accumulated carriers
Solution Approach 1:
The patent segments the gate control functions by providing a first gate for general carrier control and a second gate specifically positioned to control carrier discharge from the drift layer region. This segmentation enables the second gate to efficiently manage carrier removal from the floating layer during turn-off, resolving the discharge difficulty while maintaining the floating layer's conduction benefits
Solution Approach 2:
The invention changes the control parameters by introducing a second gate with specific voltage control capability that targets carrier discharge. By adjusting the second gate voltage independently, the patent enables precise control over carrier removal timing and rate, overcoming the discharge difficulty associated with p-type floating layers while maintaining their conduction advantages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the reduction of both turn-off loss Eoff and saturation voltage Vce (sat) simultaneously, improving the trade-off between these two critical parameters.
Implementation Method 1
a trench electrode provided in a trench formed in the upper surface, a trench insulating film provided between the trench electrode and the semiconductor substrate, a MOS electrode provided over the semiconductor substrate near the trench electrode, and a MOS insulating film provided between the MOS electrode and the semiconductor substrate
Data Source
AI summary
According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench electrode provided in a trench, a trench insulating film provided between the trench electrode and the semiconductor substrate, a MOS electrode provided near the trench electrode, and a MOS insulating film provided between the MOS electrode and the semiconductor substrate, in which the semiconductor substrate includes a first semiconductor layer, a second semiconductor layer provided over the first semiconductor layer, a third semiconductor layer provided over the second semiconductor layer, a fourth semiconductor layer provided below the MOS electrode, and one and the other of fifth semiconductor layers provided on both sides of the fourth semiconductor layer, and in which the semiconductor device further includes a wiring layer that couples the one of the fifth semiconductor layers and the second semiconductor layer together.