Trench Gate IGBT Recess Width Optimization
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Solution Overview
Problem
Semiconductor devices face a tradeoff between withstanding voltage and on-voltage, and existing methods to lower on-voltage while maintaining high withstanding voltage are inefficient, particularly due to increased feedback capacity when widening the recess in insulated gate bipolar transistors (IGBTs).
Innovation Solution
A trench gate-type semiconductor device is designed with a specific ratio of recess width to base region width, allowing for effective accumulation of holes and broadening of the depletion layer, thereby reducing on-resistance and feedback capacity without the need for a carrier accumulation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the width of the recess is widened to lower on-resistance, then on-voltage is reduced, but feedback capacity Crss is increased
Solution Approach 1:
The patent applies local quality by creating a carrier accumulation layer with higher impurity concentration in a specific region between the base region and drift region. This localized high-impurity region provides conductivity modulation benefits without requiring a wide recess, thereby reducing feedback capacity while maintaining low on-voltage.
Solution Approach 2:
The patent changes the impurity concentration parameter by forming a carrier accumulation layer with impurity concentration higher than the drift region. This parameter change enables effective conductivity modulation and low on-voltage without increasing recess width, thus avoiding the increase in feedback capacity.
2Length of moving object
If a carrier accumulation layer with higher impurity concentration than drift region is formed to lower on-voltage, then on-resistance is reduced, but it becomes difficult to broaden depletion layer sufficiently
Solution Approach 1:
The patent applies local quality by forming the carrier accumulation layer in a specific position between the base region and drift region. This localized high-impurity layer provides conductivity modulation where needed, enabling low on-voltage while the depletion layer can still broaden sufficiently in the drift region for high withstanding voltage.
Solution Approach 2:
The patent introduces a new dimensional aspect by adding the carrier accumulation layer as an intermediate region between the base region and drift region. This additional layer creates a multi-zone structure that independently addresses both conductivity modulation (low on-voltage) and depletion layer broadening (high withstanding voltage).
3Object-generated harmful factors
If a carrier accumulation layer is formed to solve the tradeoff between withstanding voltage and on-voltage, then manufacturing process is increased
Solution Approach 1:
The patent merges the carrier accumulation layer formation with the existing drift region formation process. By integrating these functions into a unified structure formed through standard semiconductor fabrication techniques, the manufacturing process complexity is minimized while still achieving the dual benefits of high withstanding voltage and low on-voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves a sufficient balance between withstanding voltage and on-voltage while reducing feedback capacity, enabling efficient conductivity modulation and improved operational performance.
Implementation Method 1
a control electrode, which is arranged on the insulation film on a side surface of the recess and faces the third semiconductor region
Implementation Method 2
a first semiconductor region, which has a first conductivity type; a second semiconductor region, which has a second conductivity type and is arranged on the first semiconductor region; a third semiconductor region, which has the first conductivity type and is arranged on the second semiconductor region; a fourth semiconductor region, which has the second conductivity type and is arranged on the third semiconductor region
Data Source
AI summary
A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess that extends from an upper surface of the fourth semiconductor region and reaches the second semiconductor region with penetrating the fourth semiconductor region and the third semiconductor region; a control electrode, which is arranged on the insulation film on a side surface of the recess and faces the third semiconductor region; a first main electrode, which is electrically connected to the first semiconductor region, and a second main electrode, which is electrically connected to the fourth semiconductor region, wherein a ratio of a width of the recess to a width of the third semiconductor region contacting the second main electrode is 1 or larger.