Trench Gate IGBT With Segmented Control Electrodes
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Solution Overview
Problem
The miniaturization of power transistors, such as IGBTs, faces challenges in reducing on-resistance and gate resistance, which hinders performance improvements and increased operation speed.
Innovation Solution
The semiconductor device design includes control electrodes and interconnects disposed in specific directions on the semiconductor substrate, allowing for independent enlargement of gate interconnects, reducing gate resistance, and dividing gate and base layers to enhance carrier injection and reduce on-resistance, thereby improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of power transistor is shrunk, then device integration is improved, but on-resistance and gate resistance increase making it difficult to reduce them
Solution Approach 1:
The gate structure is segmented into a planar gate and a trench gate, with control electrodes disposed in trenches. This segmentation allows independent optimization of each gate component, enabling the trench gate to provide additional carrier injection paths that reduce on-resistance while the planar gate maintains low gate resistance through enlarged interconnects.
Solution Approach 2:
The invention transitions from a conventional planar gate to a three-dimensional structure by disposing control electrodes in trenches. This dimensional change adds vertical carrier injection paths through the trench gates, increasing the effective gate area without expanding the planar footprint, thus reducing on-resistance while maintaining device compactness.
2Volume of moving object
If the size of power transistor is shrunk, then device integration is improved, but operation speed decreases
Solution Approach 1:
By segmenting the gate into planar and trench components with separate control electrodes, the invention enables independent control of carrier injection timing and magnitude. The trench control electrodes can be activated to provide additional carrier injection paths, reducing transit time and improving operation speed despite miniaturization.
Solution Approach 2:
The three-dimensional trench gate structure provides additional vertical carrier injection paths that shorten the effective carrier transit distance through the base region. This dimensional addition compensates for the reduced device dimensions, maintaining high operation speed in miniaturized transistors.
3Reliability
If gate interconnects are enlarged, then gate resistance is reduced, but device area increases
Solution Approach 1:
The invention moves gate interconnects into the vertical dimension by disposing them in trenches. This allows enlargement of the gate interconnect cross-sectional area in the vertical direction without increasing the planar device footprint, thereby reducing gate resistance while maintaining compact device area.
Solution Approach 2:
The gate interconnects are nested within the trench structures, utilizing the vertical space inside the trenches for interconnect placement. This nesting arrangement allows for enlarged interconnect dimensions that reduce gate resistance without consuming additional planar device area.
Data Source
AI summary
In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, control electrodes disposed in trenches on the first main surface of the semiconductor substrate and extending in a first direction parallel to the first main surface, and control interconnects disposed on the first main surface of the semiconductor substrate and extending in a second direction perpendicular to the first direction. The semiconductor substrate includes a first semiconductor layer of a first conductivity type, second semiconductor layers of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, third semiconductor layers of the first conductivity type disposed on surfaces of the second semiconductor layers on the first main surface side and extending in the second direction, and a fourth semiconductor layer of the second conductivity type on the second main surface of the semiconductor substrate.