Trench-Gate IGBT Carrier Storage Layout for Short-Circuit Tolerance

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Solution Overview

Problem

The introduction of a carrier storage layer in insulated gate bipolar transistors (IGBTs) reduces the collector-emitter saturation voltage but decreases the short-circuit tolerance, making the device more susceptible to breakdown during short-circuit events.

Innovation Solution

A semiconductor device structure is implemented with a carrier storage layer of specific impurity concentration between the base layer and the drift layer, along with a trench gate structure and a collector layer, where the impurity concentration of the carrier storage layer is limited to 1.4E16/cm3 or less adjacent to the trench, and the contact layer is deeper than the emitter layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a carrier storage layer with high impurity concentration is provided between the base layer and drift layer, then the collector-emitter saturation voltage is reduced, but the short-circuit tolerance decreases

Engineering Contradiction:

Improvecollector-emitter saturation voltageVSAvoidshort-circuit tolerance

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent applies local quality by creating different impurity concentration zones within the carrier storage layer. The region adjacent to the trench has low impurity concentration (1.4E16/cm³ or less) to maintain short-circuit tolerance, while other regions can have higher impurity concentrations to reduce collector-emitter saturation voltage. This spatial variation in impurity concentration allows simultaneous optimization of both parameters.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The carrier storage layer is segmented into regions with different impurity concentrations. By dividing the layer into a trench-adjacent region (low concentration) and other regions (higher concentration), the patent resolves the contradiction between reducing saturation voltage and maintaining short-circuit tolerance. The segmentation allows each region to fulfill its specific function without compromising the other.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If the impurity concentration of the carrier storage layer is increased, then the carrier storage effect is enhanced, but the device becomes more susceptible to breakdown during short-circuit events

Engineering Contradiction:

Improvecarrier storage capacityVSAvoidbreakdown susceptibility during short-circuit

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent implements local quality by establishing different impurity concentration levels in different spatial regions of the carrier storage layer. The trench-adjacent region maintains low impurity concentration (1.4E16/cm³ or less) to prevent breakdown during short-circuit, while other regions can have higher concentrations to enhance carrier storage capacity. This resolves the contradiction between carrier storage effectiveness and short-circuit robustness.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250151300A1Semiconductor device

Publication Date: 2025.05.08 MITSUBISHI ELECTRIC CORP

AI summary

A semiconductor device includes: an emitter layer and a contact layer that are provided in a surface portion of a base layer; a carrier storage layer provided between the base layer and a drift layer; and a trench reaching a position deeper than the carrier storage layer and having a gate electrode buried therein. A depth of the contact layer is deeper than that of the emitter layer. An impurity concentration of the carrier storage layer is 1.4E16/cm3 or less at least in a portion adjacent to the trench.