Trench Gate Insulation Structure for High-Voltage Power Semiconductors
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Solution Overview
Problem
Existing power semiconductor devices face challenges in achieving high voltage resistance and high-speed switching operations, particularly in environments requiring superior voltage resistance characteristics compared to silicon, such as power conversion and power converters.
Innovation Solution
The power semiconductor device incorporates a multi-layer gate insulating structure with varying thicknesses and dielectric constants, including a high-κ second gate insulating layer and a third gate insulating layer with a thicker bottom surface to alleviate electric field concentration and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-layer gate insulating structure is used, then the device structure is simple, but the electric field concentration causes gate insulating layer destruction and reduces reliability
Solution Approach 1:
The gate insulating layer is divided into three separate layers (first, second, and third gate insulating layers) with different dielectric constants and thicknesses. This segmentation allows each layer to perform specific functions: the first layer provides baseline insulation, the second high-κ layer reduces electric field concentration, and the third layer provides additional protection, collectively improving reliability without requiring a single complex material
Solution Approach 2:
The third gate insulating layer is configured with non-uniform thickness, being thicker at the bottom surface of the gate trench and thinner at the sidewalls. This local quality variation concentrates the protective effect where the electric field is strongest (at the bottom), while maintaining device performance at the sidewalls. The high-κ second layer is strategically positioned to specifically address electric field concentration issues
2Strength
If the gate insulating layer thickness is increased uniformly, then the insulation strength is improved, but the electric field concentration at critical regions is not alleviated and device performance deteriorates
Solution Approach 1:
The third gate insulating layer implements non-uniform thickness distribution, being thicker at the bottom surface of the gate trench where electric field concentration is most severe, and thinner at the sidewalls. This local quality approach provides enhanced insulation strength precisely where needed to prevent breakdown, while maintaining overall device performance
Solution Approach 2:
The gate insulating structure combines three different insulating materials with different dielectric constants in a multi-layer configuration. The high-κ second gate insulating layer is specifically designed to reduce electric field concentration, while the first and third layers provide complementary insulation properties, creating a composite structure that achieves both high insulation strength and high reliability
3Reliability
If a high-κ gate insulating material is used, then the electric field concentration is reduced, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
The gate insulating structure is segmented into three layers that can be fabricated using standard semiconductor processing techniques. By dividing the complex high-κ structure into manageable layers with different characteristics, each layer can be deposited and controlled using established processes, making the overall high-κ implementation manufacturable
Solution Approach 2:
The invention optimizes multiple parameters including the dielectric constants of each layer, the thickness of each layer (particularly the non-uniform thickness of the third layer), and the material composition. These parameter changes are carefully tuned to achieve the desired electric field distribution while remaining compatible with existing manufacturing capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves electrical characteristics by reducing the risk of gate insulating layer destruction and enhancing reliability, allowing for improved power semiconductor performance in high voltage and high current environments.
Implementation Method 1
The first gate insulating layer has a first dielectric constant. The second gate insulating layer has a second dielectric constant, greater than the first dielectric constant.
Implementation Method 2
The third gate insulating layer has a first thickness on a bottom surface of the gate trench and a second thickness, less than the first thickness, on a sidewall of the gate trench
Data Source
AI summary
A power semiconductor device includes a substrate of a first conductivity type, a drift layer of a first conductivity type on the substrate, a well region of a second conductivity type on the drift layer, a source region of the first conductivity type on the well region, a gate electrode disposed in a gate trench penetrating through the source region and the well region, a first gate insulating layer, a second gate insulating layer, and a third gate insulating layer sequentially disposed between the well region and the gate electrode, a dielectric layer on the gate electrode, and a drain electrode on a lower surface of the substrate.