Trench Gate Insulating Layer Layout for Withstand Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The thickness of the first dielectric layer in existing semiconductor power device manufacturing methods affects charge depletion at the bottom of the groove, impacting the withstand voltage of the device.
Innovation Solution
A manufacturing method involving multiple insulating layers and etching processes forms a second groove with a reduced depth and increased width, allowing for gate formation without thickness limitations, ensuring gate quality and maintaining withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the thickness of the first dielectric layer is increased to ensure gate quality, then the gate quality is improved, but the withstand voltage of the semiconductor power device is reduced due to increased charge depletion at the bottom of the groove
Solution Approach 1:
The patent divides the original single dielectric layer into multiple insulating layers (first insulating layer, second insulating layer, third insulating layer) with different functions and thicknesses. The first insulating layer at the bottom has optimized thickness to minimize charge depletion and maintain withstand voltage, while upper insulating layers provide sufficient total thickness for gate quality. This segmentation allows independent optimization of each layer's thickness to resolve the contradiction between gate quality and withstand voltage.
2Reliability
If the thickness of the first dielectric layer is reduced to maintain withstand voltage, then the withstand voltage is improved, but the gate quality deteriorates
Solution Approach 1:
The patent segments the dielectric structure into multiple layers where the first insulating layer at the bottom has reduced thickness to maintain withstand voltage, while additional second and third insulating layers are added above to provide sufficient total thickness for gate quality. This allows the bottom layer to be thin (maintaining voltage) while the total structure remains thick (ensuring quality).
Solution Approach 2:
Different insulating layers are assigned different local functions and thicknesses: the first insulating layer at the groove bottom has optimized thickness for electrical performance (withstand voltage), while upper layers provide structural support and total thickness for gate quality. Each layer's thickness is locally optimized for its specific function, resolving the global contradiction.
3Device complexity
If a single thick dielectric layer is used, then the process is simple, but the charge depletion at the bottom of the groove increases, affecting withstand voltage
Solution Approach 1:
The patent segments the dielectric layer into multiple insulating layers with different thicknesses, where the bottom layer is thinner to reduce charge depletion. Although this increases structural complexity, it resolves the electrical performance issue. The segmented structure allows precise control of electric field distribution and charge depletion at the groove bottom.
4Reliability
If multiple insulating layers are used to resolve the thickness contradiction, then both gate quality and withstand voltage are improved, but the device structure becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the dielectric structure into multiple insulating layers with distinct functions. The first insulating layer at the bottom has optimized thickness for electrical performance, while upper layers provide structural completeness. This segmentation resolves the electrical contradiction while managing structural complexity through functional differentiation of each layer.
Solution Approach 2:
Each insulating layer is assigned local quality characteristics - different thicknesses and positions - to optimize specific functions. The bottom layer prioritizes electrical performance, while upper layers provide structural support. This local optimization allows the system to achieve both gate quality and withstand voltage without uniform complexity throughout the structure.
Data Source
AI summary
A manufacturing method of a semiconductor power device includes the following steps: An n-type substrate is etched in a self-aligning manner using a first insulating layer, a second insulating layer, and a third insulating layer as a mask to form a second groove in the n-type substrate. A fourth insulating layer and a gate are formed in the second groove.