Trench-Gate LDMOS Layout for Low On-Resistance and High Breakdown
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Solution Overview
Problem
Conventional LDMOS transistors face challenges in achieving low on-resistance and high breakdown voltage simultaneously, which is crucial for efficient power switching applications.
Innovation Solution
The development of LDMOS transistors with multiple gate conductors and trench structures, where one or more gate structures are partially formed in a trench, promotes low on-resistance and high breakdown voltage by optimizing dopant concentrations and dielectric layers, allowing for a reduced surface field effect and enhanced current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional LDMOS transistor structure with single gate is used, then manufacturing is simpler, but on-resistance cannot be sufficiently reduced
Solution Approach 1:
The gate structure is divided into multiple gate conductors (first gate conductor and second gate conductor) that are disposed at different lateral positions. This segmentation allows independent optimization of each gate region, enabling reduced on-resistance through multiple current paths while maintaining manufacturing feasibility through systematic fabrication processes.
Solution Approach 2:
The invention transitions from a single-plane gate structure to a multi-dimensional configuration where gate conductors are arranged both laterally (different x-positions) and vertically (different z-heights in the trench). This dimensional expansion provides additional degrees of freedom for optimizing electrical characteristics without proportionally increasing manufacturing complexity.
2Reliability
If multiple gate conductors are used to reduce on-resistance, then on-resistance decreases, but device complexity increases
Solution Approach 1:
Multiple gate conductors are merged into a single integrated gate structure that functions as one cohesive unit. The gate conductors share common gate dielectric layers and are controlled by a single gate electrode, combining multiple functional elements into a unified structure that reduces control complexity while maintaining electrical performance benefits.
Solution Approach 2:
The multi-conductor gate structure serves multiple functions simultaneously: it provides multiple current conduction paths for reduced on-resistance, maintains high breakdown voltage through optimized electric field distribution, and enables independent regional control for enhanced device performance. This multi-functionality justifies the increased structural complexity.
3Reliability
If gate structures are formed in trench to optimize performance, then breakdown voltage increases, but manufacturing precision requirements increase
Solution Approach 1:
The trench structure is segmented to accommodate multiple gate conductors at different lateral positions, with each segment optimized for specific electrical characteristics. This segmentation allows gradual implementation and verification of trench formation processes, reducing the overall precision burden compared to forming a single complex structure.
Solution Approach 2:
The invention optimizes trench parameters (depth, width, shape) and gate conductor parameters (position, dimensions, spacing) to achieve high breakdown voltage while maintaining manufacturability. By carefully selecting and adjusting these parameters, the design balances performance requirements with manufacturing precision capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces on-resistance while maintaining high breakdown voltage, making the transistors suitable for high-performance power switching applications with improved efficiency and reliability.
Implementation Method 1
A positive voltage VGS applied between gate electrode 116 and source electrode 104 creates negative charges in silicon semiconductor structure 102 under silicon dioxide layer 118, causing a minority-carrier channel to form
Implementation Method 2
When positive voltage VDS is applied across drain electrode 108 and source electrode 104, a p-n junction at the interface of n-well 124 and p-body 126 is reversed biased. Consequentially, essentially no current flows from drain electrode 108 to source electrode 104 by default
Data Source
AI summary
A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure, a dielectric layer at least partially disposed in a trench of the silicon semiconductor structure in a thickness direction, and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction. The dielectric layer and the gate conductor are at least substantially symmetric with respect to a center axis of the trench extending in the thickness direction, as seen when the LDMOS transistor is viewed cross-sectionally in a direction orthogonal to the lateral and thickness directions.