Trench Gate Structure With Low-k Shielding for Oxide Breakdown Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Trench gate semiconductor devices face reliability issues due to high voltage stress, which can lead to breakdown of the oxide layer at the bottom of the trench gate, exacerbating the risk of electrical failure.
Innovation Solution
The implementation of an amorphous semiconductor layer with a low dielectric constant material wrapped around the outer bottom wall and corners of the gate, combined with a shield layer forming a PN junction, reduces the voltage borne by the gate insulator and enhances the breakdown field strength, thereby improving the reliability of the oxide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trench gate structure is used to achieve high electron mobility and low JFET resistance, then on resistance is reduced, but the oxide layer at the bottom of the trench gate bears high electric field stress, increasing breakdown risk
Solution Approach 1:
An amorphous semiconductor layer with low dielectric constant is introduced as an intermediary between the gate insulator and the high-voltage environment. This layer acts as a mediator that reduces the electric field stress concentrated on the gate insulator, particularly at the bottom of the trench gate, thereby preventing oxide layer breakdown while maintaining the low on-resistance benefit of the trench gate structure
Solution Approach 2:
The dielectric constant parameter of the material at the gate bottom is changed by using an amorphous semiconductor layer with low dielectric constant instead of the conventional high-dielectric constant material. This parameter change reduces the electric field concentration and stress on the gate insulator, solving the reliability issue without sacrificing the electrical performance of the trench gate device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively enhances the reliability of the trench gate semiconductor device by reducing the electric field stress on the gate insulator, improving its breakdown field strength and overall device performance.
Implementation Method 1
an amorphous semiconductor layer is formed in the first trench and wraps an outer bottom wall of the gate and corners on two sides of the outer bottom wall in a manner of being separated by the gate insulator, where the amorphous semiconductor layer is made of a low dielectric constant material
Implementation Method 2
the trench gate semiconductor device further includes a shield layer having the second conductivity type, formed on the epitaxial layer at a bottom of the first trench, where the shield layer wraps the amorphous semiconductor layer, and extends in an arc chamfer to the gate insulator on the corners or side walls of the gate. The shield layer can form a PN junction with the substrate
Data Source
AI summary
A trench gate semiconductor includes a substrate having a first conductivity type; an epitaxial layer having the first conductivity type, grown on the substrate; a well region having a second conductivity type, formed on a surface layer of the epitaxial layer; a source region having the first conductivity type, formed on a surface layer of the well region; a first trench, running through the well region from a surface of the source region to the epitaxial layer; a gate, formed in the first trench in a manner of being separated by a gate insulator; and an amorphous semiconductor layer, formed in the first trench and wrapping an outer bottom wall of the gate and corners on two sides of the outer bottom wall in a manner of being separated by the gate insulator, where the amorphous semiconductor layer is made of a low dielectric constant material.