Trench Gate Semiconductor Layout for Lower Miller Capacitance
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Solution Overview
Problem
Existing semiconductor designs face challenges in achieving low conduction and switching losses due to high Miller capacitance and difficulties in extracting charge carriers from p-type doped regions, especially when switching from the ON-state to the OFF-state.
Innovation Solution
The semiconductor device incorporates a design with closely packed trench gate electrodes and a fortified layer of the second conductivity type, which reduces hole drainage and improves reverse bias blocking performance, while minimizing the area of gate electrodes to reduce Miller capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If p-type doped regions are used to enhance charge carrier plasma concentration in the ON-State, then electron-hole concentration is improved, but extraction of electric charges from these regions becomes difficult, generating significant turnoff losses
Solution Approach 1:
The patent applies local quality by creating a fortified layer with higher doping concentration in specific regions adjacent to the trench gates. This localized enhancement facilitates more efficient extraction of charge carriers from p-type doped regions during turnoff, reducing turnoff losses while maintaining improved electron-hole plasma concentration in the ON-state through the same fortified structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves reduced conduction and switching losses, improved controllability, and reliability by minimizing Miller capacitance and facilitating efficient charge carrier extraction, thereby enhancing the overall performance of power semiconductors.
Implementation Method 1
The first gate electrodes are insulated by a first insulation layer from the material of the drift layer
Implementation Method 2
source regions of the first conductivity type having a doping density higher than said drift layer, and formed by ion implantation through a source lithography mask
Data Source
AI summary
A semiconductor device with an active transistor cell comprising a p-doped first and second base layers, surrounding an n type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional fortifying p-doped layers embedding the opposite ends of the trench recesses. The additional fortifying layers do not affect the active cell design in terms of cell pitch i.e., the design rules for transistor cell spacing, or hole drainage between the transistor cells, but reduce the gate-collector parasitic capacitance of the semiconductor, hence leading to optimum low conduction and switching losses. To further reduce the gate-collector capacitance, the trench recesses embedding the first gate electrodes can be formed with thicker insulating layers in regions that do not abut the first base layers, so as not to negatively impact the value of the threshold voltage.