Trench Gate MOS Reducing Mirror Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Trench gate type IGBTs with floating p-type regions face challenges in controllability of turn-on di/dt due to increased mirror capacitance and difficulty in forming intricate patterns due to surface level differences caused by gate electrodes on the substrate front surface.
Innovation Solution
A semiconductor device design featuring a trench gate type MOS gate structure with a floating p-type region, where a second gate electrode covers the floating p-type region across an insulation layer, reducing mirror capacitance and allowing for the formation of intricate patterns by minimizing surface level differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a gate electrode is provided across a gate insulating film on the substrate front surface side surface of the floating p-type region, then controllability of turn-on di/dt improves, but mirror capacitance increases remarkably
Solution Approach 1:
The gate electrode is extracted from the substrate front surface side and relocated to the substrate back surface side. This removes the source of excessive mirror capacitance while preserving the controllable potential rise effect on the floating p-type region through the trench gate structure.
Solution Approach 2:
The gate electrode positioning is changed from the front surface (2D plane) to the back surface (opposite 2D plane), utilizing the third dimension (depth) to resolve the contradiction between controllability and capacitance.
2Quantity of substance
If LOCOS is used to eliminate mirror capacitance increase, then mirror capacitance is reduced, but a large difference in level of the element front surface is caused
Solution Approach 1:
The gate electrode is extracted from the front surface region entirely and placed on the back surface, eliminating the need for LOCOS isolation structures and their associated surface level differences.
Solution Approach 2:
By moving the gate electrode to the back surface, the front surface remains flat and suitable for intricate patterning, while the back surface accommodates the gate structure that would otherwise cause surface level issues.
3Ease of operation
If a gate electrode is drawn out onto the substrate front surface side surface of the floating p-type region, then controllability of turn-on di/dt improves, but formation of element structure with intricate pattern becomes difficult
Solution Approach 1:
The gate electrode is extracted from the front surface area, clearing the way for intricate pattern formation while maintaining controllability functions through the trench gate and back surface electrode configuration.
Solution Approach 2:
The gate electrode is relocated to the back surface dimension, freeing the front surface for complex patterning operations while the gate electrode on the back surface continues to provide controllable potential modulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves controllability of turn-on di/dt, reduces mirror capacitance, and enables the formation of complex patterns on the semiconductor device surface, enhancing manufacturing feasibility and device performance.
Implementation Method 1
a gate insulating film provided on a trench side wall... a displacement current in accordance with the gate-collector capacitance flows into the floating p-type region via the gate electrode
Implementation Method 2
a second gate electrode covers the floating p-type region across an insulation layer, reducing mirror capacitance
Data Source
AI summary
A trench gate type MOS gate structure is provided in an active region on a substrate front surface side, and a floating p-type region is provided in a mesa region between trenches. A groove is provided distanced from the trench in a surface layer on the substrate front surface side of the floating p-type region. A second gate electrode is provided across an insulation layer in the interior portion of the groove. The second gate electrode covers the surface on the substrate front surface side of the floating p-type region. Thus, the second gate electrode is embedded in a surface layer on the substrate front surface side of the floating p-type region between the floating p-type region and an interlayer dielectric, whereby the substrate front surface is flattened. Controllability of turn-on di/dt is high, mirror capacitance is low, and an element structure having an intricate pattern can be formed.