Trench-Gate MOSFET Doping Layout for Low On-Resistance Reliability
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Solution Overview
Problem
Power semiconductor devices with thick p+ -type semiconductor regions experience increased on resistance, while thin regions can degrade the reliability of the gate insulation film, and varying dimensions lead to inconsistent performance.
Innovation Solution
A MOSFET semiconductor device with a trench-gate structure, where the p-type semiconductor region has a lower impurity concentration than the p+ -type semiconductor region, and the n-type semiconductor regions are strategically positioned to mitigate the electric field on the gate insulation film, reducing on resistance and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the p+ -type semiconductor region is made thick to reduce on resistance, then the on resistance decreases, but the reliability of the gate insulation film degrades due to increased electric field stress
Solution Approach 1:
The patent applies local quality by creating distinct regions with different impurity concentrations within the p-type semiconductor layer. Specifically, it forms a p-type semiconductor region with higher impurity concentration and a p+ -type semiconductor region with lower impurity concentration, allowing each region to fulfill different functional requirements: the high-concentration region provides low on-resistance while the low-concentration region reduces electric field stress on the gate insulation film
Solution Approach 2:
The patent changes the impurity concentration parameter within the p-type semiconductor layer to resolve the contradiction. By varying the impurity concentration from high (in the p-type region) to low (in the p+ -type region), the patent achieves both low on-resistance and reduced electric field stress, thereby simultaneously improving conductivity and gate insulation film reliability
2Reliability
If the p+ -type semiconductor region is made thin to improve gate insulation film reliability, then the gate insulation film reliability improves, but the on resistance increases
Solution Approach 1:
The patent creates functionally differentiated regions within the p-type semiconductor layer, where the p-type region with higher impurity concentration compensates for the reduced thickness of the p+ -type region by providing additional conductive pathways, thus maintaining low on-resistance while allowing the p+ -type region to be thin enough to protect the gate insulation film
Solution Approach 2:
The patent effectively creates a composite semiconductor structure by combining regions with different impurity concentrations (p-type and p+ -type regions) within the same semiconductor layer. This composite structure allows the device to exhibit both the low resistance characteristics of highly doped regions and the electric field management benefits of lightly doped regions
3Loss of energy
If the dimensions of the p-type and p+ -type semiconductor regions are varied to optimize performance, then the on resistance can be optimized, but the manufacturing precision requirements increase
Solution Approach 1:
The patent segments the p-type semiconductor layer into distinct regions (p-type semiconductor region and p+ -type semiconductor region) with different impurity concentrations. This segmentation allows independent optimization of each region's properties and simplifies the manufacturing process, as each region can be formed with standard doping techniques rather than requiring precise control of continuous dimensional variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses the electric field on the p+ -type semiconductor region, maintaining low on resistance and improving the reliability of the gate insulation film, while reducing the reverse transfer capacitance and on resistance.
Implementation Method 1
the n-type semiconductor regions are strategically positioned to mitigate the electric field on the gate insulation film
Implementation Method 2
A MOSFET semiconductor device with a trench-gate structure, where the p-type semiconductor region has a lower impurity concentration than the p+ -type semiconductor region, and the n-type semiconductor regions are strategically positioned
Data Source
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AI summary
A semiconductor device according to an embodiment includes a gate electrode extending in a first direction, a gate insulation film that covers the gate electrode, a first semiconductor region of a first conductivity type extending in a second direction orthogonal to the first direction below the gate insulation film, and a second semiconductor region of the first conductivity type that faces the gate insulation film across the first semiconductor region. An impurity concentration of the first conductivity type of the second semiconductor region is lower than that of the first semiconductor region.