Trench-Gate MOSFET Grid Layout for Lower Gate Resistance
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Solution Overview
Problem
Existing power trench-gate MOSFETs have high gate terminal resistance, which affects electrical performance, reliability, and robustness, particularly in applications requiring stringent electrical performance and fault tolerance.
Innovation Solution
The MOSFET design features a grid-like layout of gate stripes intersecting in the active area, with uniformly distributed gate regions extending in both x and y directions, reducing mechanical stresses and increasing the number of gate contacts and parallel resistances, thereby enhancing the conduction channel perimeter and fault tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional linear gate stripe layout is used, then manufacturing is simpler, but gate resistance is high and electrical performance is poor
Solution Approach 1:
The gate structure is segmented into multiple intersecting gate stripes forming a grid pattern, where gate stripes in the first direction and gate stripes in the second direction cross each other to create multiple gate contacts. This segmentation increases the number of parallel conduction paths, reducing gate resistance and improving electrical performance while maintaining manufacturability through standardized trench formation processes.
2Reliability
If gate stripes extend only in one direction, then manufacturing is easier, but gate resistance remains high due to fewer parallel paths
Solution Approach 1:
The gate stripe layout transitions from a one-dimensional linear arrangement to a two-dimensional grid structure by adding gate stripes in a second direction that intersects with the first direction. This dimensional expansion creates multiple intersection points serving as gate contacts, increasing parallel resistance paths and reducing overall gate resistance while using the same trench depth and basic formation processes.
3Reliability
If fewer gate contacts are used, then device structure is simpler, but fault tolerance and robustness are reduced
Solution Approach 1:
Multiple gate stripes in both directions are merged into a single integrated gate structure sharing common gate metallization and control signals. The intersecting gate stripes form a unified grid where all regions are electrically connected through the gate metallization layer, providing redundant conduction paths that enhance fault tolerance while maintaining single-gate control simplicity.
Data Source
AI summary
A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.