Trench-Gate MOSFET Layout for High Cell Density and Low ON Resistance
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Solution Overview
Problem
Existing trench-gate MOSFETs face a trade-off between cell density and ON resistance due to the inclusion of a p-type buried region between adjacent trenches, leading to increased ON resistance.
Innovation Solution
A trench-gate insulated gate semiconductor device with a configuration that includes a carrier transport layer, injection control region, trenches, and buried regions of specific conductivity types, along with a high-concentration region, to enhance cell density while minimizing ON resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type buried region is provided in the middle between the trenches adjacent to each other to relax the electric field intensity at the bottom of the trench, then the gate insulating film damage is prevented, but the cell density decreases and the ON resistance increases
Solution Approach 1:
The patent applies local quality by providing the p-type buried region only at specific locations (bottom of trenches and selectively between adjacent trenches) rather than uniformly across the entire structure. This localized approach allows the electric field relaxation function to be performed where needed while minimizing the impact on cell density and ON resistance.
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing a high-concentration region with higher impurity concentration than the carrier transport layer. This parameter change allows for improved electrical characteristics and reduced ON resistance while maintaining the protective function of the buried regions.
2Reliability
If a p-type buried region is provided in the middle between the trenches adjacent to each other to relax the electric field intensity, then the gate insulating film is protected from damage, but the ON resistance increases
Solution Approach 1:
The patent provides the p-type buried region selectively at the bottom of trenches and only between certain adjacent trenches, rather than uniformly between all trenches. This localized configuration protects the gate insulating film where electric field stress is highest while minimizing the impact on ON resistance by reducing the total area occupied by the buried regions.
Solution Approach 2:
The introduction of a high-concentration region with higher impurity concentration compensates for the increased ON resistance caused by the buried regions. This parameter change in impurity concentration improves carrier transport and reduces the overall ON resistance while maintaining the protective function.
3Productivity
If the cell density is increased to reduce the ON resistance, then the manufacturing efficiency improves, but the electric field intensity at the bottom of the trench increases causing gate insulating film damage
Solution Approach 1:
The patent applies local quality by concentrating the p-type buried regions at critical locations (bottom of trenches and selectively between adjacent trenches) where electric field stress is highest. This allows for higher cell density overall while providing targeted protection to the gate insulating film at the most vulnerable points.
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing a high-concentration region that compensates for the increased electric field intensity resulting from higher cell density. This parameter change allows the device to achieve both high cell density and reliable gate insulating film protection.
Data Source
AI summary
An insulated gate semiconductor device includes: a carrier transport layer of a first conductivity-type; an injection control region of a second conductivity-type; a carrier supply region of the first conductivity-type; a base contact region of the second conductivity-type; trenches penetrating the injection control region to reach the carrier transport layer; an insulated gate structure provided inside the respective trenches; an upper buried region of the second conductivity-type being in contact with a bottom surface of the injection control region; a lower buried region of the second conductivity-type being in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches; and a high-concentration region of the first conductivity-type provided inside the carrier transport layer to be in contact with a part of a bottom surface of the lower buried region.