Trench Gate Semiconductor Layout for Gate Oxide Field Concentration
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Solution Overview
Problem
Conventional semiconductor devices with trench structures experience dielectric breakdown due to field concentration on the bottom portion of the gate insulating layer when a reverse bias is applied, leading to reduced withstand voltage.
Innovation Solution
A semiconductor device design featuring a trench structure where the second semiconductor layer has an extended portion closer to the second face, with a channel region and additional semiconductor regions formed to mitigate field concentration, including a recessed portion and additional semiconductor regions to reduce impurity concentration and prevent punch-through phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a trench structure is used with a gate insulating layer formed along the inner wall, then the device can achieve vertical stacking and compact structure, but field concentration occurs on the bottom portion of the gate insulating layer causing dielectric breakdown
Solution Approach 1:
The patent applies local quality by creating an extended portion of the second semiconductor layer with different impurity concentration (lower impurity concentration) specifically at the region where field concentration occurs (bottom portion of gate insulating layer). This localized modification of material properties addresses the field concentration problem without changing the overall trench structure design.
Solution Approach 2:
The patent changes the impurity concentration parameter in the second semiconductor layer by forming an extended portion with lower impurity concentration compared to the main body. This parameter change modifies the electrical characteristics to reduce field concentration and prevent dielectric breakdown while maintaining the vertical stacking structure.
2Reliability
If the second semiconductor layer is extended closer to the second face to reduce field concentration, then dielectric breakdown is suppressed, but the threshold voltage decreases
Solution Approach 1:
The extended portion with lower impurity concentration is formed only in the specific region where field concentration occurs, while the main body of the second semiconductor layer maintains its original impurity concentration. This localized approach allows threshold voltage control in the extended region without significantly affecting the overall device threshold voltage.
Solution Approach 2:
The extension of the second semiconductor layer is performed to a specific extent (partial action) - extending closer to the second face but not completely reaching it. This partial extension is sufficient to reduce field concentration and suppress dielectric breakdown while minimizing the impact on threshold voltage.
3Reliability
If additional semiconductor regions with different conductivity types are formed, then field concentration is distributed and dielectric breakdown is prevented, but device structure becomes more complex
Solution Approach 1:
The patent merges the extended portion of the second semiconductor layer with the existing trench structure and gate insulating layer. The extended portion is integrated into the overall device architecture, forming a unified structure that distributes field concentration without requiring completely separate additional components.
Data Source
AI summary
A semiconductor device includes a semiconductor layer having a first face with a trench formed thereon and a second face opposite to the first face, a gate electrode, and a gate insulating layer. The semiconductor layer includes a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer, and an n-type semiconductor region. The trench is formed to penetrate through the p-type semiconductor layer and to reach the second n-type semiconductor layer. The p-type semiconductor layer includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench is. Such structure allows suppressing dielectric breakdown in the gate insulating layer.