Trench Gate Oxide Profile for GIDL-Resistant Semiconductor Structures
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Solution Overview
Problem
The reduction in semiconductor device size without a corresponding decrease in working voltage leads to significant gate-induced-drain-leakage (GIDL) current effects, affecting the reliability of semiconductor devices.
Innovation Solution
A method is employed to form a semiconductor structure by creating a trench in a substrate, filling it with a sacrificial dielectric layer, gradually etching and oxidizing the sidewall to form an oxide dielectric layer with varying thickness, and forming a conductive layer within the trench to reduce GIDL by optimizing the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of semiconductor device is decreased to scale down, then the integration density is improved, but the gate-induced-drain-leakage (GIDL) current effect increases due to strong electric field in short channel device
Solution Approach 1:
The patent applies local quality by creating a gate dielectric layer with non-uniform thickness distribution. The thickness varies from a first thickness at the gate electrode interface to a second thickness at the interface with the semiconductor substrate, with an intermediate thickness in between. This local variation in dielectric thickness optimizes the electric field distribution locally, reducing GIDL current at critical regions while maintaining device scaling.
Solution Approach 2:
The patent changes the physical parameter of gate dielectric thickness from a uniform value to a graded distribution. By controlling the thickness parameter to vary continuously or in steps from the gate electrode toward the substrate, the electric field strength is modulated, thereby reducing GIDL current effect while preserving the scaled-down device dimensions.
2Length of stationary object
If the oxide layer thickness is reduced to 2 nm or less to enable device scaling, then the device size is decreased, but the GIDL current effect is enhanced due to stronger electric field
Solution Approach 1:
Instead of using a uniformly thin oxide layer (2 nm or less) throughout, the patent implements local quality by varying the oxide thickness spatially. The region adjacent to the gate electrode has a different thickness than the region near the substrate, creating optimal electric field control at each location and suppressing GIDL current while maintaining overall device scaling.
Solution Approach 2:
The patent transitions from a one-dimensional uniform thickness model to a multi-dimensional thickness profile. By introducing thickness variation along the vertical dimension (from gate electrode to substrate interface), the solution addresses the GIDL problem without requiring further reduction in the minimum oxide thickness at critical locations.
3Area of moving object
If the working voltage is maintained at the same level while device size is scaled down, then the device density is improved, but the GIDL current effect increases due to strong electric field
Solution Approach 1:
The patent changes the electric field distribution parameter by implementing a graded gate dielectric thickness profile. This parameter modification allows the device to operate at the same voltage while scaling down, as the varying thickness optimizes field control and reduces the harmful GIDL current effect that would otherwise result from the compressed dimensions.
Solution Approach 2:
By applying local quality through spatially varying dielectric thickness, the patent addresses the GIDL current generation at specific high-field regions while maintaining the overall scaled-down device geometry and operating voltage, thus reducing harmful effects without sacrificing integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The varying thickness of the oxide dielectric layer reduces GIDL, enhancing the reliability and stability of the semiconductor device by minimizing current leakage and parasitic capacitance.
Implementation Method 1
the sidewall of the trench is oxidized to form an oxide dielectric layer
Data Source
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AI summary
Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The method includes the following operations. A trench is formed in a substrate. A sacrificial dielectric layer is filled in the trench. The sacrificial dielectric layer is etched gradually to gradually expose a sidewall of the trench, and at least part of the exposed sidewall of the trench is oxidized to form an oxide dielectric layer, in which a thickness of the oxide dielectric layer in the trench gradually increases in a direction extending from a bottom to an opening of the trench. A conductive layer is formed on a surface of the oxide dielectric layer and the conductive layer is formed in the trench.