Trench Gate Oxide Thickening to Reduce UMOSFET Capacitance
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Solution Overview
Problem
Existing gate fabrication methods for UMOSFETs face challenges in achieving a thicker gate oxide layer at the trench bottom, leading to limited breakdown voltages and increased parasitic gate-drain capacitance due to electric field crowding and corner enhancement effects.
Innovation Solution
A modified gate fabrication method involving thermal oxidation of polysilicon sidewalls with a barrier layer to suppress lateral oxidation, resulting in a thicker oxide layer at the trench bottom and reduced parasitic gate-drain capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal oxidation is performed on polysilicon sidewalls without barrier layer, then oxide layer thickness increases, but lateral oxidation occurs causing poor process control
Solution Approach 1:
A barrier layer is deposited on the polysilicon sidewalls before thermal oxidation to prevent lateral oxidation. This preliminary protective action ensures that during subsequent oxidation steps, the oxide grows only vertically at the trench bottom without spreading laterally, thereby achieving precise oxide thickness control while simplifying process management
Solution Approach 2:
The barrier layer acts as an intermediary between the polysilicon sidewall and the oxidizing environment. It selectively allows vertical oxide growth at the trench bottom while blocking lateral oxidation on the sidewalls, enabling independent control of oxide thickness at different locations without complex process parameters
2Manufacturing precision
If gate oxide layer is formed by thermal oxidation on (0001) crystal plane, then oxidation rate is lower, but this causes thinner oxide at trench bottom compared to sidewall
Solution Approach 1:
The barrier layer creates different oxidation conditions at different locations: at the trench bottom where the (0001) plane is exposed, oxide grows vertically with controlled thickness; on the sidewalls where the (11-20) plane would normally oxidize rapidly, the barrier layer prevents lateral oxidation. This local differentiation achieves uniform oxide thickness despite crystallographic orientation differences
Solution Approach 2:
The barrier layer is applied in advance to counteract the naturally higher oxidation rate of the (11-20) sidewall crystal plane. By blocking lateral oxidation pathways before they can occur, the barrier layer prevents the sidewall oxide from becoming thicker than the bottom oxide, ensuring thickness uniformity across different crystal orientations
3Reliability
If trench depth exceeds P-well to enter N- drift region, then complete channel formation is achieved, but electric field crowding occurs at gate bottom corners reducing breakdown voltage
Solution Approach 1:
The thermal oxidation process rounds the sharp corners at the gate bottom by growing oxide preferentially at high-curvature regions. This curvature modification reduces electric field crowding at the corners, thereby increasing breakdown voltage while maintaining the required trench depth for complete channel formation
Solution Approach 2:
The oxidation process changes the geometric parameters of the gate structure by rounding corners and reducing radius of curvature at the gate bottom. This parameter change directly addresses the electric field crowding issue, allowing the transistor to achieve both complete channel formation and improved breakdown voltage
4Reliability
If polysilicon sidewalls are fully oxidized without barrier layer, then oxide fills the trench completely, but parasitic gate-drain capacitance increases
Solution Approach 1:
The barrier layer on the polysilicon sidewalls acts as a spatial mediator that controls oxide distribution. It allows oxide to fill the trench bottom vertically while blocking oxide from depositing on the sidewalls. This results in partial trench filling that reduces gate-drain overlap and parasitic capacitance, while maintaining precise control over oxide placement
Solution Approach 2:
The oxide filling is segmented into two distinct regions: a vertical oxide layer at the trench bottom that provides electrical isolation, and no oxide on the sidewalls that reduces parasitic capacitance. The barrier layer enables this segmentation by selectively permitting oxidation at the bottom while preventing it on the sidewalls
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively increases the oxide thickness at the trench bottom, reduces trench corner curvature, and decreases parasitic gate-drain capacitance, thereby enhancing breakdown voltages and reliability of power transistors.
Implementation Method 1
a barrier layer covering the polysilicon sidewall is adopted for suppressing its lateral oxidation
Implementation Method 2
the polysilicon sidewalls are oxidated
Data Source
AI summary
A fabrication method for increasing bottom gate oxide thickness of a power transistor and trench gate structure formed by using the same are provided. A power transistor is provided, and a gate oxide layer is deposited along its trench. Two polysilicon sidewalls are formed and covering thereon. A barrier layer is provided on a side surface of each polysilicon sidewall. And wet etching process is used to remove the gate oxide layer underneath such that a vacancy is formed at the bottom of the trench. By oxidizing the polysilicon sidewalls, a thick oxide layer is formed and filling the vacancy. The disclosed barrier layer is used for avoiding the polysilicon sidewalls from lateral oxidation such that the process method is under better process control. By employing the present invention, it is advantageous of increasing bottom gate oxide thickness, reducing trench corner curvature as well as parasitic gate-drain capacitance.