Trench Gate-Controlled Pin Switch With Charge Trapping Dielectric
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Solution Overview
Problem
Conventional two-carrier power semiconductor devices, such as IGBTs and MCTs, face challenges in high voltage applications due to high on-state voltage drop and high turn-off energy, as well as low controllable current capability at high blocking voltages, making them inadequate for high efficiency power electronic systems.
Innovation Solution
A normally off trench gate-controlled p-i-n switch with a charge trapping material in the gate dielectric and a self-depleted channel is developed, featuring a gate dielectric with three layers and a trench structure that includes a lightly doped channel and heavily doped regions, allowing for low on-state voltage drop and reduced turn-off energy through optimized plasma distribution and doping concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If conventional two-carrier power semiconductor devices (IGBT, MCT) are used in high voltage systems, then high voltage blocking capability is achieved, but on-state voltage drop and turn-off energy increase significantly
Solution Approach 1:
The device is segmented into distinct functional regions: a lightly doped channel region for low on-state voltage drop, a charge trapping layer for controlled carrier storage, and a drift region for high voltage blocking. This segmentation allows each region to be optimized independently, achieving low power loss while maintaining high voltage capability.
Solution Approach 2:
The invention changes the doping concentration parameter from uniform (conventional) to non-uniform with a lightly doped channel region, and introduces a charge trapping layer with specific trap density. These parameter changes enable the device to maintain high voltage blocking capability while reducing on-state voltage drop and turn-off energy through optimized plasma distribution.
2Stress or pressure
If IGBT is scaled into high voltages (600-6000 V), then high voltage blocking capability is improved, but on-state voltage drop and turn-off energy worsen
Solution Approach 1:
The channel region is designed with local quality characteristics - lightly doped specifically in the channel area to reduce on-state voltage drop, while the drift region maintains appropriate doping for high voltage blocking. The charge trapping layer is positioned locally to control plasma distribution where needed, enabling the device to scale to high voltages without proportionally increasing power losses.
3Stress or pressure
If MCT is used at high blocking voltage, then high voltage capability is achieved, but controllable current capability deteriorates
Solution Approach 1:
The charge trapping layer acts as an intermediary between the gate control electrode and the channel-drift region. It provides controlled carrier storage and release, enabling precise control of current capability at high blocking voltages. This intermediary layer allows the device to overcome the limited controllable current capability of conventional MCT while maintaining high voltage capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low power loss with both low on-state voltage drop and turn-off energy, enabling efficient operation in high voltage power electronic systems by maintaining high plasma concentration near the junction and reducing backside injection efficiency, while ensuring a high threshold voltage for reliable operation.
Implementation Method 1
a charge trapping material in the gate dielectric
Implementation Method 2
an inversion layer is formed at a surface of the gate dielectric between the gate electrode and the first doped region based on an amount of fixed charges included in the charge trapping material
Implementation Method 3
a fully depleted state is established in the channel
Data Source
AI summary
The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with a low on-state voltage drop and a low turn-off energy. In an aspect, a power semiconductor device is provided that embodies a normally off trench gate-controlled p-i-n switch with a charge trapping material in the gate dielectric and a self-depleted channel.