Trench Gate High-Voltage Transistor for Planarization Uniformity
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Solution Overview
Problem
The integration of high voltage devices in embedded memory ICs faces challenges such as poor device height uniformity due to dishing effects and gate metal loss during planarization, leading to sheet resistance and threshold voltage variations.
Innovation Solution
The implementation of a trench gate high voltage transistor design, where the logic gate dielectric and electrode are positioned within a trench, reducing lateral device area and protecting the top surface from planarization processes, thereby maintaining device integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If planarization process is used to flatten the substrate surface, then surface flatness is improved, but gate metal loss and device height uniformity deteriorate
Solution Approach 1:
The gate structure is transitioned from a planar configuration to a three-dimensional trench gate structure. The gate electrode is positioned within a trench etched into the substrate, allowing the gate to extend vertically along the trench walls. This dimensional change enables the gate metal to be protected from planarization damage while still achieving surface flatness, as the trench structure accommodates the gate metal without requiring it to be removed during planarization processes.
2Manufacturing precision
If trench gate structure is implemented, then device height uniformity and gate metal protection are improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple components: a trench structure etched into the substrate, a gate dielectric layer lining the trench walls, and a gate electrode positioned within the trench. This segmentation allows each component to be optimized independently - the trench provides mechanical support and protection, the dielectric ensures electrical isolation, and the electrode provides the gating function. The segmented structure achieves device uniformity while managing complexity through functional decomposition.
3Area of stationary object
If lateral device area is reduced by trench gate design, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrode is nested within the trench structure, which itself is nested within the substrate. This nested configuration allows the gate metal to be positioned deep within the substrate structure, protected from surface planarization processes. The nesting approach reduces the lateral footprint of the device while the vertical trench structure accommodates the gate components, achieving high integration density without excessively stringent manufacturing precision requirements.
Data Source
AI summary
Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC is manufactured by forming a plurality of deep trenches including an isolation trench and a logic device trench from a top surface of a substrate, filling an isolation material in the isolation trench and the logic device trench, removing the isolation material from the logic device trench, forming a first logic device by filling a first logic gate dielectric and a first logic gate electrode in the logic device trench, and forming first and second source/drain regions in the substrate on opposite sides of the logic device trench. The isolation material is kept in the isolation trench to form an isolation structure.