Trench Gate Layout for Compact Vertical Power Semiconductors
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Solution Overview
Problem
Existing vertical semiconductor power devices face limitations in miniaturization due to the large area occupied between trenches and source contacts, resulting from the minimum line width of photolithography, which increases device size and resistance.
Innovation Solution
A vertical semiconductor power device design where the gate electrode is placed in trenches surrounded by a dielectric layer, reducing the distance between trenches and the total surface area, and incorporating gate electrode connectors to minimize resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate electrode is placed on the mesa top between trenches and source contacts, then the device structure is simple to manufacture, but the area occupied between trenches and source contacts increases, limiting device miniaturization
Solution Approach 1:
The gate electrode is moved from the horizontal plane (mesa top) to the vertical dimension (inside the trench), surrounding the shield electrode in a three-dimensional configuration. This dimensional transition eliminates the need for horizontal spacing between gate electrodes and source contacts, thereby reducing the occupied area while maintaining manufacturing feasibility through standard trench formation processes.
Solution Approach 2:
The gate electrode is positioned inside the trench to surround the shield electrode, creating a nested configuration where the gate electrode encompasses the shield electrode vertically. This nesting approach allows the gate electrode to be contained within the existing trench structure without requiring additional horizontal space, thus reducing the area between trenches and source contacts.
2Area of stationary object
If the distance between trenches is reduced for miniaturization, then the total surface area decreases, but the manufacturing precision requirements increase due to photolithography limitations
Solution Approach 1:
By relocating the gate electrode into the vertical space within the trench, the design eliminates the need for precise horizontal positioning of gate electrodes relative to source contacts. The trench depth provides the necessary separation, allowing reduced trench spacing without compromising manufacturing precision requirements.
3Device complexity
If the gate electrode directly adjoins the shield electrode and substrate, then the device complexity is reduced, but the resistance increases
Solution Approach 1:
The dielectric layer is introduced as an intermediary between the gate electrode and the shield electrode/substrate. This intermediate layer provides electrical isolation that prevents direct contact, thereby reducing resistance while maintaining a relatively simple overall device structure that integrates seamlessly with the trench configuration.
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A vertical semiconductor power device is provided, which includes a substrate having a first surface and a second surface opposite to each other. A trench extends from the second surface toward the first surface. An in-trench dielectric layer is disposed along an inner surface of the trench. A shield electrode is disposed in the trench and is surrounded by the in-trench dielectric layer. A gate electrode is disposed in the in-trench dielectric layer and surrounds the shield electrode. The gate electrode is surrounded by the in-trench dielectric layer without adjoining the shield electrode and the substrate. A method for making the vertical semiconductor power device is also provided.